topic Re: about CTS_B signal with DTE mode for i.MX6Solo in i.MX Processors

about CTS_B signal with DTE mode for i.MX6Solo

yuuki — Tue, 09 Feb 2016 03:09:09 GMT

Dear all,

We use UART of i.MX6 as DTE mode.

We understand that the CTS_B can be set in HIGH or LOW by setting CTSC bit and the CTS bit of the UCR2 register.

However, when RXEN bit was set to 0, a value of CTS_B seemed to become HIGH forcibly regardless of these register setting.

Is the CTS_B signal affected by other register setting (except the CTS bit)?

Best Regards,
Yuuki

Re: about CTS_B signal with DTE mode for i.MX6Solo

Yuri — Tue, 09 Feb 2016 05:20:33 GMT

Hello,

In DTE mode signals are implemented as shown on figure of section 64.2 (External Signals)

of the i.MX6 S/DL RM. The CTS is mapped to RTS.

Have a great day,
Yuri

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Re: about CTS_B signal with DTE mode for i.MX6Solo

yuuki — Tue, 09 Feb 2016 06:58:34 GMT

Dear Yuri-san,

Thank you for your quick response.

I referred to the following URL.
https://community.freescale.com/docs/DOC-97509

In this URL,
for DTE mode, UART_CTS_B is connected to Output CTS_B.

Is this a mistake?

Best Regrds,
Yuuki

Re: about CTS_B signal with DTE mode for i.MX6Solo

Yuri — Tue, 09 Feb 2016 07:18:32 GMT

I agree with comment of martin-schad
(in i.MX6: What does the DTE/DCE in i.MX6's UART do and how are RTS and CTS affected by the UARTxUFCR[DTEDCE] bit? ) :
"But it seems that there is a typo in your table. In my opinion, DCE/DTE text in your table must be swapped."

Regards,

Yuri.

Re: about CTS_B signal with DTE mode for i.MX6Solo

yuuki — Tue, 09 Feb 2016 10:27:43 GMT

Dear Yuri-san,

Thank you for your support.
I'm sorry. I overlooked it.

However, there is a question more.

In DTE Mode, RTS_B of UART IP port(inside of iMX6) is connected to UART_CTS_B of IO port.
And, Direction of RTS_B of UART IP port is Input.
I do not know why does UART CTS_B of IO port become High when RXEN bit is set to 0.

May I have advice?

Best Regards,
Yuuki

Re: about CTS_B signal with DTE mode for i.MX6Solo

Yuri — Fri, 12 Feb 2016 03:08:28 GMT

Hello,

What is IOMUX configuration for UART functionality ?

In particular is IOMUXC_UART1_UART_RTS_B_SELECT_INPUT (for UART1)
is selected correctly ?

Is SION bit set ? (say in IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 for UART1) ?

Regards,

Yuri.

Re: about CTS_B signal with DTE mode for i.MX6Solo

yuuki — Thu, 18 Feb 2016 11:30:13 GMT

Dear Yuri-san,

Thank you for your support.

I confirmed those registers.

- IOMUXC_UART1_UART_RTS_B_SELECT_INPUT : 0x1

- IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 : 0x4

May I have advice?

Best Regards,

Yuuki

Re: about CTS_B signal with DTE mode for i.MX6Solo

Yuri — Mon, 22 Feb 2016 07:43:01 GMT

Hello,

In Your configuration internal CTS (output) signal is routed to external pin

UART1_UART_RTS_B (mux-ed with EIM_DATA20).

Please check if this pin is properly connected. Also, please check if all internal UART

module clocks are active.

Regards,

Yuri.

Re: about CTS_B signal with DTE mode for i.MX6Solo

yuuki — Fri, 04 Mar 2016 07:26:50 GMT

Dear Yuri-san,

Thank you for your support.

I'm sorry for the delay in my response.

We have a problem about UART2 and UART3 not UART1.

[UART2] EIM_D28(pin G23) is used as CTS_B(ALT4)

- IOMUXC_UART2_UART_RTS_B_SELECT_INPUT：0x0

- IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28：0x4

[UART3] EIM_D30(pin J20) is used as CTS_B(ALT4)

- IOMUXC_UART3_UART_RTS_B_SELECT_INPUT：0x1

- IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30：0x4

When the RXEN bit of the UCR2 register is set to 0, CTS_B become HIGH.

Why is CTS_B driven to High by RXEN=0?

Because it is DTE mode, RTS_B of UART IP port is connected to IO port of UART_CTS_B.

We understand that it does not drive the IO port, because RTS_B of UART IP is Input.

Best Regards,

Yuuki

Re: about CTS_B signal with DTE mode for i.MX6Solo

shubhamsanghvi — Tue, 08 Mar 2016 11:20:47 GMT

Hello,

The behavior that is expected from the CTS_B pin should be observed on the RTS_B pin of the UART IO port in DTE mode.

So, additional IOMUX settings that needs to be made are :

1. IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29：0x4 (UART2 RTS_B)

2. IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31：0x4 (UART3 RTS_B)

After this, changing the CTSC bit and the CTS bit in UCR2 should affect the RTS_B pin of UART IO i.e.(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29).

Also, The RTS_B pin of UART IP port is an active low pin. So, Ideally it should remain high when the UART is enabled which is probably why the CTS_B of UART IO port is getting high.

But the change of CTS_B (UART IO) on clearing RXEN is a bit unusual. You could check if TXEN or UARTEN bits affect the value of CTS_B (UART IO) or not.

As per my understanding the only difference in the DTE/DCE mode is the signal routing. Making the external UART connection according to the new routed signals should make it work.

Thanks,

Shubham

Re: about CTS_B signal with DTE mode for i.MX6Solo

marcocavallini — Wed, 20 Apr 2016 15:03:48 GMT

Is it your board (UART) now working properly with RTS/CTS signals?

From the linux kernel point of view, are these registers set through DeviceTree settings, or you needed to modify any .C code (imx.c)?

And finally, would you mind to share your DeviceTree excerpt in order to clearly understand what did you do to solve this issue?

Thank you