<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Question, NAND chip TC58NVG0S3 use for i.MX25 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493792#M79353</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A while ago, we received the answer on Toshiba/TC58NVG0S3 NAND chip use for i.MX25 from this community as below.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/379638"&gt;https://community.freescale.com/thread/379638&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And it says that Toshiba/TC58NVG0S3 NAND flash chip cannot meet the specification of i.MX25 NFC.&lt;/P&gt;&lt;P&gt;We found the description table entry of “TC58NVG0S3” in your LinuxBSP, L2.6.31_09.12.00, source code.&lt;/P&gt;&lt;P&gt;It is written in nand_device_info_table_type_2[] structure in drivers/mtd/nand/nand_device_info.c file in the LinuxBSP.&lt;/P&gt;&lt;P&gt;If the code has not been tested, I mean whether the table entry of TC58NVG0S3 can really work is not sure,&lt;/P&gt;&lt;P&gt;Then Can I understand the NAND chip might be used as NAND device under the Linux but the NAND chip still cannot be used for Boot device?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 18 Dec 2015 06:56:15 GMT</pubDate>
    <dc:creator>Aemj</dc:creator>
    <dc:date>2015-12-18T06:56:15Z</dc:date>
    <item>
      <title>Question, NAND chip TC58NVG0S3 use for i.MX25</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493792#M79353</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A while ago, we received the answer on Toshiba/TC58NVG0S3 NAND chip use for i.MX25 from this community as below.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/379638"&gt;https://community.freescale.com/thread/379638&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And it says that Toshiba/TC58NVG0S3 NAND flash chip cannot meet the specification of i.MX25 NFC.&lt;/P&gt;&lt;P&gt;We found the description table entry of “TC58NVG0S3” in your LinuxBSP, L2.6.31_09.12.00, source code.&lt;/P&gt;&lt;P&gt;It is written in nand_device_info_table_type_2[] structure in drivers/mtd/nand/nand_device_info.c file in the LinuxBSP.&lt;/P&gt;&lt;P&gt;If the code has not been tested, I mean whether the table entry of TC58NVG0S3 can really work is not sure,&lt;/P&gt;&lt;P&gt;Then Can I understand the NAND chip might be used as NAND device under the Linux but the NAND chip still cannot be used for Boot device?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 18 Dec 2015 06:56:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493792#M79353</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2015-12-18T06:56:15Z</dc:date>
    </item>
    <item>
      <title>Re: Question, NAND chip TC58NVG0S3 use for i.MX25</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493793#M79354</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; The main restriction for TC58NVG0S3 with i.MX25 NFC relates to possible reliability&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;issues, since when considering NAND datasheet (in the Community thread) I found&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;information about page = (2K + 128) bytes and 8-bit ECC ; but the i.MX25 NFC uses &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;for such NANDs 4-bit ECC.&amp;nbsp; &lt;BR /&gt; Nevertheless, today I found the TC58NVG0S3 Datasheet, where there is no such &lt;BR /&gt; statement about 8-bit ECC. So, please consult with the manufacturer if TC58NVG0S3 &lt;BR /&gt; page organization of (2K + 128) can be reliably used with 4-bit ECC. If so – yes we &lt;BR /&gt; can use this NAND with i.MX25.&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 Dec 2015 08:37:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493793#M79354</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-12-21T08:37:18Z</dc:date>
    </item>
    <item>
      <title>Re: Question, NAND chip TC58NVG0S3 use for i.MX25</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493794#M79355</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your comment.&lt;/P&gt;&lt;P&gt;Could you show me the boot-pin settings for supporting page=(2K + 128) bytes NAND?&lt;/P&gt;&lt;P&gt;Or can I understand such NAND which has a page-size of (2K+128)bytes still cannot be used for boot?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Dec 2015 05:52:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493794#M79355</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2015-12-28T05:52:45Z</dc:date>
    </item>
    <item>
      <title>Re: Question, NAND chip TC58NVG0S3 use for i.MX25</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493795#M79356</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;* BT_PAGE_SIZE[1:0]&amp;nbsp; = 01 (2K)&lt;/P&gt;&lt;P&gt;* BT_BUS_WIDTH =&amp;nbsp; 00 (8-bit)&lt;/P&gt;&lt;P&gt;* BT_SPARE_SIZE = 0&amp;nbsp; (128 bytes)&lt;/P&gt;&lt;P&gt;* BT_MEM_TYPE[1:0] = 01&amp;nbsp; (4 address cycles)&lt;/P&gt;&lt;P&gt;* BT_MLC_SEL - you may try both SLC or MLC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 Jan 2016 05:32:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-NAND-chip-TC58NVG0S3-use-for-i-MX25/m-p/493795#M79356</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-01-08T05:32:39Z</dc:date>
    </item>
  </channel>
</rss>

