i.MX ProcessorsのトピックRe: IMX6 TskewT

IMX6 TskewT

inderjitbains — Sun, 10 Apr 2016 06:16:14 GMT

Section 4.11.5.3 of IMX6DQIEC, Table 58 states that TskewT is -100 to +900 ps. Is this instead of the nominal +/- 500 ps, i.e. a delay of 400ps? Is this adjustable in a register or fixed?

Note 3 states that this implies a TXC delay at the PHY of 1.2ns to 1.7ns instead of the nominal 1.5ns to 2.0ns - shouldn't this be 1.1ns to 1.6ns, if the TSC delay is 400ps?

Note 3 also says that this is for all versions of RGMII prior to 2.0. What if the PHY is RGMII 2.0? Does the PHY just add the delay instead of implementing the delay on the PCB?

Re: IMX6 TskewT

igorpadykov — Mon, 11 Apr 2016 01:14:43 GMT

Hi Inderjit

- this delay option is not configurable in i.MX6 ENET.

A delay should be implemented at the board level.

- what is "TSC delay" ? Seems this additional board delay should not

depend on any delay, since it just adds timing for compliance with

ver.1.3 RGMII specification.

- i.MX6 ENET is compliant with RGMII 1.3.

Regarding RGMII 2.0 PHY it is working fine with i.MX6 ENET,

I am not sure if delay can be implemented in PHY, seems it

is necessary to verify with its datasheet and perform ibis

modelling.

Best regards

igor

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Re: IMX6 TskewT

inderjitbains — Mon, 11 Apr 2016 01:43:38 GMT

As long as the delay is constant at 400ps, the remaining delay can be added in the PHY instead of adding an additional delay at the board level (longer trace). Can you confirm that it is constant at 400ps?

Re: IMX6 TskewT

igorpadykov — Mon, 11 Apr 2016 02:04:36 GMT

could you clarify what is "delay is constant at 400ps" ?

Re: IMX6 TskewT

inderjitbains — Mon, 11 Apr 2016 03:25:27 GMT

Section 4.11.5.3 of IMX6DQIEC, Table 58 states that TskewT is -100 to +900ps. Normally, this is -500ps to +500ps. -100ps to +900ps is the same as adding a 400ps delay. Can you confirm that a TskewT of -100ps to +900ps will effectively delay RGMII_TXC by 400ps, and that -100ps to +900ps are the lower and upper bounds from -40C to +85C?

Re: IMX6 TskewT

inderjitbains — Mon, 11 Apr 2016 04:58:06 GMT

Also, is DDR_SEL in IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII set to b11 in u-boot for Sabre SD, since NVCC_RGMII is 1.5V? Or is it left at the default b10 (1.2V)?

For DSE in IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, the default is b110. This is 37 ohms, too low for most boards. Is it set anywhere in u-boot?

I did a grep for IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII and IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC and found nothing.

Re: IMX6 TskewT

igorpadykov — Mon, 11 Apr 2016 06:22:56 GMT

yes, "TskewT of -100ps to +900ps will effectively delay RGMII_TXC by 400ps".

Table 62. RGMII Signal Switching Specifications provides timings

-100ps to +900ps for full temperature range specified by datashet.

IMX6DQIEC rev.4 7_2015.pdf document in Table 6. Operating Ranges

defines Junction temperature -40 :- 105C.

For DSE in IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC suggest to create

new thread.

Best regards

igor