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    <title>topic Re: Question, i.MX6SoloLite power-up sequence in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-power-up-sequence/m-p/492292#M79067</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Miyamoto&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;according to datasheet Power-Up Sequence requirements (below)&lt;/P&gt;&lt;P&gt;there are only some restrictions for VDD_ARM_IN, SOC_IN&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/59411i6413EDAF9D83AF0F/image-size/large?v=v2&amp;amp;px=999" role="button" title="1.jpg" alt="1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 05 Feb 2016 08:59:08 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-02-05T08:59:08Z</dc:date>
    <item>
      <title>Question, i.MX6SoloLite power-up sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-power-up-sequence/m-p/492291#M79066</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to ask about the power-up sequence of i.MX6SoloLite.&lt;/P&gt;&lt;P&gt;Are there any restriction on the power-up order of VDD_ARM_IN, SOC_IN, PU_IN and VDD_HIGH_IN?&lt;/P&gt;&lt;P&gt;Can I understand that there is no matter whatever the power-up order of VDD_ARM_IN, SOC_IN, PU_IN and VDD_HIGH_IN is?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Feb 2016 07:47:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-power-up-sequence/m-p/492291#M79066</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-02-05T07:47:41Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite power-up sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-power-up-sequence/m-p/492292#M79067</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Miyamoto&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;according to datasheet Power-Up Sequence requirements (below)&lt;/P&gt;&lt;P&gt;there are only some restrictions for VDD_ARM_IN, SOC_IN&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/59411i6413EDAF9D83AF0F/image-size/large?v=v2&amp;amp;px=999" role="button" title="1.jpg" alt="1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Feb 2016 08:59:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-power-up-sequence/m-p/492292#M79067</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-02-05T08:59:08Z</dc:date>
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