topic Re: About setup/hold time of synchronous display in i.MX6DQ. in i.MX Processors

About setup/hold time of synchronous display in i.MX6DQ.

keitanagashima — Thu, 17 Dec 2015 01:53:57 GMT

Dear All,

Hello. We wasnt to calculate the setup/hold time of synchronous display in i.MX6DQ.

Refer to "Figure 71. Synchronous Display Interface Timing Diagram—Access Level" and "Table 70. Synchronous Display Interface Timing Characteristics (Access Level)" in IMX6DQAEC(Rev.4).

[Q1]

From Table 70;

Tdsu (min) = Tdicd - 1.24 , Tdsu (typ) = Tdicu

Tdhd (min) = Tdicp-Tdicd-1.24 , Tdhd (typ) = Tdicp-Tdicu

But, the relation looks Tdsu (min) > Tdsu (typ).

I think that Tdsu (min) = Tdicu - 1.24, and also Tdhd (min) = Tdicp-Tdicu-1.24.

Is the value of Table.70 right?

[Q2]

Does "IPP_DATA" shift in the local start point?

[Q3]

Are "Display interface clock down time(Tdicd)" and "Display interface clock up time(Tdicu)" defined at the time from local start point in Figure 69?

Best Regards,

Keita

Re: About setup/hold time of synchronous display in i.MX6DQ.

art — Thu, 17 Dec 2015 11:47:27 GMT

Q. Is the value of Table.70 right?

A. Yes.

Q. Does "IPP_DATA" shift in the local start point?

A. No.

Q. Are "Display interface clock down time(Tdicd)" and "Display interface clock up time(Tdicu)" defined at the time from local start point in Figure 69?

A. Actually, these parameters mean the display clock edge fall time and display clock edge rise time, so, there is no any "absolute" time relation here.

Have a great day,
Artur

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Re: About setup/hold time of synchronous display in i.MX6DQ.

keitanagashima — Fri, 18 Dec 2015 09:13:41 GMT

Dear Artur,

Hello. Thank you for your reply.

But, I couldn't understand your answer.

> A. Actually, these parameters mean the display clock edge fall time and display clock edge rise time,

> so, there is no any "absolute" time relation here.

Is the "display clock edge fall time" (= Tdicd) defined where to where?

I couldn't see it from Figure 71.

Let me know specifically.

Best Regards,

Keita

Re: About setup/hold time of synchronous display in i.MX6DQ.

art — Thu, 24 Dec 2015 08:16:40 GMT

The display clock edge fall time is the time between the points where the clock signal starts and ends its transition from High to Low state.

Best Regards,

Artur

Re: About setup/hold time of synchronous display in i.MX6DQ.

keitanagashima — Mon, 28 Dec 2015 04:18:35 GMT

Dear Artur,

Thank you for your reply.

I illustrate my question in attached file..

Please check again.

Best Regards,

Keita

Re: About setup/hold time of synchronous display in i.MX6DQ.

art — Mon, 28 Dec 2015 12:09:16 GMT

What do you mean as "local start point"? Please specify in more details.

Best Regards,

Artur

Re: About setup/hold time of synchronous display in i.MX6DQ.

keitanagashima — Tue, 29 Dec 2015 00:10:08 GMT

Dear Artur,

Refer to "4.11.10.6.1 IPU DisplayOperating Signals" in IMX6DQAEC Rev.4.

- All synchronous display controls are generated on the base of an internally generated “local start point”.

And, “local start point” is illustrated in Figure 69 & Figure 71 of IMX6DQAEC Rev.4.

Best Regards,

Keita

Re: About setup/hold time of synchronous display in i.MX6DQ.

art — Mon, 25 Jan 2016 10:30:54 GMT

Let me answer your questions according to the Excel sheet you've attached earlier.

Q1. Is the Tdicu (Data setup time) time between local start point and rising edge of IPP_DISP_CLK?

Is the Tdicd (Data holdup time) time between local start point and falling edge of IPP_DISP_CLK?

A1. Actually, the right naming of these parameters is as follows: Tdicu is the

Display Interface Clock Up Time, and Tdicd is the Display Interface Clock Down

Time. The meaning of these parameters is as you describe: Tdicu is the time

between the local start point and the display clock up edge, and Tdicd is

the time between the local start point and the display clock down edge. The

meaning of up and down edges (i.e. whether the up edge is the rising

one and down edge is the falling one or vice versa) depends on the clock

polarity setting.

Q2. Is Figure 71 right? I think that Tdicu and Tdicd are opposite.

A2. The 1st paragraph of the Section 4.11.10.6.3 "TFT Panel Sync Pulse Timing

Diagrams" (bottom of the Page 104) of the IMX6DQAEC Rev.4 document says the

following.

"The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal

and active-low polarity of the HSYNC, VSYNC, and DRDY signals".

So, according to that, the polarity of the display clock is set to inverted, and the Figure 71 is correct.

Q3. Why does the data sheet define "Tdicd-1.24"? Refer to <Figure B>.

Why does the deta sheet define "Tdicp -Tdicd-1.24"? Refer to <Figure C>.

A3. Again, the confusing factor there is that the display clock is shown inverted,

see above. In that case, the Clock Up edge is shown as the falling one, and the

Clock Down edge - as the rising one. The timebase for the Tdsu and Tdhd times is

still the local start point.

Best Regards,

Artur