topic Re: DDR Address Mirror Issues in i.MX Processors

DDR Address Mirror Issues

tony_l_cai — Thu, 17 Dec 2015 08:18:04 GMT

Hi all,

What's meaning about the DDR Address Mirror?

Could you give me a sample in ddr application? In other word, when will use it?

Re: DDR Address Mirror Issues

igorpadykov — Thu, 17 Dec 2015 09:12:44 GMT

Hi Tony

"DDR Address Mirror" means that some DDR signals

change (as described in Table 44-6. Address mirroring options i.MX6DQ RM

rev.3 7/2015), for example :

DRAM_A3 appears as DRAM_A3 for Chip select 0 and

as DRAM_A4 signal Chip select 1.

This is useful for for easy board DDR routing. From software point of

view there are no changes.

Best regards

igor

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Re: DDR Address Mirror Issues

tony_l_cai — Sun, 20 Dec 2015 06:22:04 GMT

Dear igor,

From the following article, I seem to understand a little that the address mirroring can make the pin connect to each other to make the layout so simple, But I still don't know why can do that. Why won't all these pins connect to each other make any error?

DDR3 memory mirroring - PCB layout - Welldone Blog - FEDEVEL

Could you give more and futher illustration?