i.MX ProcessorsのトピックRe: iMX6 GPIO state during Startup & Power Sequencing https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488676#M78282 <HTML><HEAD></HEAD><BODY><P>Thank You Igor!</P></BODY></HTML> Wed, 30 Mar 2016 12:55:28 GMT ndsonu 2016-03-30T12:55:28Z iMX6 GPIO state during Startup & Power Sequencing https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488674#M78280 <HTML><HEAD></HEAD><BODY><P>Hello All,</P><P></P><P>We have a custom board based on i.MX6 (Quad), processor: IMX6 Quad, revision: C. It is powered from PMIC PF0100. We found glitches on few GPIO lines (Ball Name: DI0_PIN2, Ball No: N25) during start up and also noticed that these glitches have relation to power sequencing.</P><P><STRONG style="text-decoration: underline;">Scenario 1:</STRONG></P><P>Following is the power sequence:</P><OL><LI>VDDARM_IN, VDDSOC_IN</LI><LI>NVCC_XXX lines</LI><LI>NVCC_DRAM</LI><LI><SPAN style="color: red;">VDD_SNVS_IN, VDDHIGH_IN</SPAN></LI></OL><P>On this sequence we see a glitch (unwanted toggling) on the DI0_PIN2 during start up. Please see the attached waveform</P><P><STRONG style="text-decoration: underline;">Scenario 2:</STRONG></P><P>Following is the power sequence:</P><OL><LI><SPAN style="color: red;">VDD_SNVS_IN</SPAN></LI><LI>VDDARM_IN, VDDSOC_IN</LI><LI><SPAN style="color: red;"> </SPAN>NVCC_XXX lines,<SPAN style="color: red;"> VDDHIGH_IN</SPAN></LI><LI>NVCC_DRAM</LI></OL><P>On this sequence we see no glitch but the pin DI0_PIN2&nbsp; which should be a HIGH due to internal 100K pull up becomes so only after a few milli seconds from RESET.</P><P><STRONG style="text-decoration: underline;">Scenario 3:</STRONG></P><P>Following is the power sequence:</P><OL><LI><SPAN style="color: red;">VDD_SNVS_IN, VDDHIGH_IN</SPAN></LI><LI>VDDARM_IN, VDDSOC_IN</LI><LI>NVCC_XXX lines,<SPAN style="color: red;"> </SPAN></LI><LI>NVCC_DRAM</LI></OL><P></P><P>On this sequence we see no glitch and pin DI0_PIN2 becomes HIGH before release of RESET.</P><P></P><P><SPAN style="text-decoration: underline;">Observation from above scenarios:</SPAN> VDD_SNVS_IN and VDDHIGH_IN should be applied to i.MX6 before any other supply rails for a glitch free GPIO transitions during reset. </P><P>Datasheet says “VDD_SNVS_IN” should be applied first. But I think not anything about “VDDHIGH_IN”.</P><P></P><P>Is my observation expected?</P><P>What is the dependency of GPIO pin on VDD_HIGH_IN?</P><P></P><P>Thanks in Advance!</P><P></P><P>Regards,</P><P>Sonu Kurian</P></BODY></HTML> Fri, 18 Mar 2016 10:16:48 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488674#M78280 ndsonu 2016-03-18T10:16:48Z Re: iMX6 GPIO state during Startup & Power Sequencing https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488675#M78281 <HTML><HEAD></HEAD><BODY><P>Hi Sonu</P><P></P><P>you are right, scenario 3 provides more glitchless behaviour,</P><P>because VDDHIGH_IN provides power for processor control logic.</P><P></P><P>Best regards</P><P>igor</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Fri, 18 Mar 2016 11:42:05 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488675#M78281 igorpadykov 2016-03-18T11:42:05Z Re: iMX6 GPIO state during Startup & Power Sequencing https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488676#M78282 <HTML><HEAD></HEAD><BODY><P>Thank You Igor!</P></BODY></HTML> Wed, 30 Mar 2016 12:55:28 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6-GPIO-state-during-Startup-Power-Sequencing/m-p/488676#M78282 ndsonu 2016-03-30T12:55:28Z