i.MX Processors中的主题 Re: ADV7280-m clock issue

ADV7280-m clock issue

kurkinalexandr — Fri, 29 Apr 2016 12:10:01 GMT

Hello.

Currently I am working on driver integration task for adv7280-m chip.

And I got issue related to mipi csi clock. Mipi dphy driver detect Clock line as ULPS(ultralow power state). You can see my oscilloscope images in this branch adv7280-M clock problem | EngineerZone .

I am trying to understand what could be the reason of issue: adv7280-m chip or imx6. Could anybody, who worked with this adv7280-m chip show me your signals on the mipi lines or analize my signals.

I also interested in what should be switched on first: the decoder chip mipi dphy or imx6 mipi dphy.

As I understand. there are a lot of people who managed to get workable adv7280-m chip with imx6. Could you also share your mipi csi2 driver settup

Thanks.

Re: ADV7280-m clock issue

igorpadykov — Fri, 29 Apr 2016 13:58:47 GMT

Hi Fan

I would suggest to configure properly i.MX6 mipi clock as described in

Debug steps for customer MIPI sensor.docx

A Simple tutor for writing i.MX6 mipi driver, use adv7480 as an example

Best regards

igor

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Re: ADV7280-m clock issue

kurkinalexandr — Fri, 29 Apr 2016 15:24:48 GMT

Hello.

Thank you for replay. I will examine the experience and patches for adv7480.

Do you know whether I will see mipi clk sygnal on the clk wire in case of wrong mipi clock configuration in imx6 processor?

Thanks.

Re: ADV7280-m clock issue

igorpadykov — Mon, 02 May 2016 00:51:22 GMT

actually adi support suggested easy way to debug that

as described in AN1337 on p.2:

manually program the clock lane of the ADV7280-M, ADV7281-M

to enter and then exit LP mode. The easiest way to do this is by

toggling the CSITX_PWRDN bit (Address 0x00, Bit 7).

Data and clock lanes can enter ulps state independently, for clock lane

one can follow comand given on p.52

http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADV7280_7281_7282_UG-637.pdf .

also please check

i.MX6Q video capture issue with ADV7280-M

~igor

Re: ADV7280-m clock issue

kurkinalexandr — Mon, 02 May 2016 11:12:26 GMT

I of course tried all of these debug steps.

See below my oscilloscope images.

1) Low state mode: CSITX_PWRDN bit (Address 0x00, Bit 7) contains 1 value.

Mipi data:

Mipi clk:

2) Switching on to high speed mode: set CSITX_PWRDN bit (Address 0x00, Bit 7) in zero value.

Mipi data in high speed mode:

Mipi clk in high speed mode:

Transient process from low power to high speed on mipi clk line:

If I switch on imx6 dphy(mipi_csi2_reset()) after clearing CSITX_PWRDN in ad7280-m, I get 0x200 in State register. If I switch on imx6 dphy before clearing CSITX_PWRDN, I get 0x210 in State register.

3) Just for experience: set both lines to ULPS mode, regarding to ADV7280_7281_7282_UG-637.pdf documet P.52

For both lines:

You can see, that MIPI lines pulled down in real ULPS mode.

I also looked through this brunch i.MX6Q video capture issue with ADV7280-M.

But I think my problem is a little be different, as I can`t see clk sygnal physically. There could be several reasons for this issue:

1) imx6 incorrect terminates mipi clk line. To exclude this version, It could be useful if anybody could show his mipi clk sygnal in case of switched off imx6 dphy and switched on dphy.

2) ad7280 incorrect pass clk sygnal. To exclude this issue I need to get example of clean mipi sygnal from ADV7280-m with disconnected from mipi slave device wires.

3) hardware issue on my board

Than you for help.

Re: ADV7280-m clock issue

kurkinalexandr — Tue, 03 May 2016 07:23:21 GMT

Hi Igor.

Do you think it is correct that transition from 1.2V to 0.1-0,2V on CLK line was detected as ULPS by imx6(0x210 in state register)?

Thanks.

Re: ADV7280-m clock issue

igorpadykov — Tue, 03 May 2016 08:12:14 GMT

I think yes it can be detected in MIPI_CSI_PHY_STATE register bit 9.

Best regards

igor

Re: ADV7280-m clock issue

kurkinalexandr — Tue, 03 May 2016 09:24:22 GMT

But ULPS mode should have 0V level on lines. In our case we have 0,1-0,2V and it is high speed level according to DPHY specification.

Re: ADV7280-m clock issue

igorpadykov — Tue, 03 May 2016 09:29:59 GMT

are you sure that this is not noise, as is ULPS mode

sensor can turn off supplies from lane.

Also this can be quality issue, so recommended to double

check behaviour on other board/sensor.

Re: ADV7280-m clock issue

kurkinalexandr — Tue, 03 May 2016 09:46:10 GMT

As I understand, imx6 should detect 1.2 >0.1V transition(low power -> high speed) and set termination on the line. If it detect this transition as ULPS, it of course will not set termination and future signal on the line will be not correct(noise in my case as you said).

Do you have any opportunity to get signal oscilloscope images in case of correct imx6-adv7280-m work?

Re: ADV7280-m clock issue

igorpadykov — Tue, 03 May 2016 11:47:12 GMT

I have not adv7280 but one can attach external termination resistors and check.

Re: ADV7280-m clock issue

kurkinalexandr — Wed, 04 May 2016 13:50:04 GMT

Unfortunately it is difficult to solder this termination resistor on our board. May be we will order ADV7280-m kit and connect it to CM-FX6 kit or Sabre board.

Could you explane me some points related to MIPI_CSI_PHY_STATE.

First of all 9-th bit. Active low. Is that mean that clk lane in ULPS if the bit equel zero value?

8-th bit. Clock lane actively receiving a DDR cloclk. Is that bit mean(1-value) that imx6 DPHY module clock is correctly configured. In my case it is always zero value.

Thanks.

Re: ADV7280-m clock issue

igorpadykov — Thu, 05 May 2016 01:58:04 GMT

please create new thread for new questions

Best regards

igor