topic IMX6 PCIe (LVDS) Termination (Data) in i.MX Processors

IMX6 PCIe (LVDS) Termination (Data)

dominicmusgrove — Thu, 25 Feb 2016 12:57:12 GMT

Hello

I am interfacing PCIe between IMX6 and a FPGA. I am a little confused with the coupling used for the IMX6 on the PCIe port.

The IMX6 clock and PCIe outputs are LVDS, the only thing the datasheet says about the LVDS I/O electrical characteristic is that it is TIA/EIA 644-A compliant.

Two questions: (This is both for the PCIe receiver not transmitter pair).

TIA/EIA 644-A compliant devices MUST have a DC bias, the common mode range is +0.2 to +2.2V, therefore why do none of the reference designs have DC bias? This could exceed the absolute maximum rating of the pin (VSS - 0.5V or VCC + 0.3V) and cause damage to the device. There is nothing motioned about allowed common-mode voltage range for any pins being anything other than stated above, or any internal DC bias to these pins. Therefore it is my understanding that external DC bias is required.

TIA/EIA 644-A compliant devices do not by default have internal 100R termination, I cannot find where stated that the PCIe inputs have internal termination, therefore why do none of the reference designs have external 100R termination?

Many thanks,

Dominic

Re: IMX6 PCIe (LVDS) Termination (Data)

igorpadykov — Fri, 26 Feb 2016 00:25:52 GMT

Hi Dominic

seems PCIe uses CML, not LVDS as for example reviewed on

LVDS, CML, ECL-differential interfaces with odd voltages | EE Times

regarding termination and electrical specs on can refer to PCISIG resources

Welcome to PCI-SIG | PCI-SIG

Best regards

igor

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Re: IMX6 PCIe (LVDS) Termination (Data)

dougplymale — Wed, 14 Dec 2016 20:38:30 GMT

Dominic,

If you haven't found out already, you will need to place 49.9 ohm termination resistors on CLKx_N and CLKx_P near the receiving chip. You will also want have the normal AC coupling capacitors near the iMX6.

Regards,

Doug