topic Re: 4GB DDR3 Support in i.MX Processors

4GB DDR3 Support

suhasdk — Thu, 04 Feb 2016 13:25:06 GMT

Hi Folks,

I have two queries to address:

Planing to use single rank 4GB DDR3 (1GB Device x 4) using single Chip Select (CS0) in one of our design. Please let us know whether i.MX6Q supports such memory organisation that is 4GB on single Chip select.
Pretty sure that i/MX6Q works fine with 533MHz DDR clock frequency. I have ambiguity in interfacing 800MHz DDR3 memory device with i.MX6. To be specific, whether MT41K512M16HA-125 IT micron device can be used in above mentioned memory organization.

Thanks & Regards,

Suhas D K

Re: 4GB DDR3 Support

MOW — Thu, 11 Feb 2016 09:59:54 GMT

Hi Suhas

Last year for testing purposes we equipped some few of our own i.MX6Q-based boards with 4pcs 8 GBit (512M16) DDR3 RAM-Chips from Intelligent Memory in 64-bit bus-configuration, i.e. all 4 chips connected to a single chip-select. Although we were not able to perform elaborate tests due to mechanical problems with the chips on our boards -- the 8 GBit chips from IM are slightly larger than all other DDR3 chips we equipped so far and unfortunately collided with some filter capacitors placed too close to the RAM-chips on the boards -- we were able to get two of the test-boards to (partially) functioning state, execute some few runtime-tests, and access the 3.75 GByte of memory mapped to the CPU-address space in such a configuration.

So, yes: 4 GByte RAM connected to a single chip-select of an i.MX6Q do work.

While we haven't done any tests with the 8 GBit Micron type K you're asking for, we're using the 2 GBit and 4 GBit versions of these RAM-types without any problems in both DDR3-1066G amd DDR3-800E configurations and RAM-chips specified for higher clock-rates can be used at these clock-rates without any issues.

As far as I know, the i.MX6 SoCs do not support any DDR3 clock-rates faster than 533 MHz (DDR3-1066).

Regards,

Marc

Re: 4GB DDR3 Support

flournoy — Tue, 28 Mar 2017 17:59:14 GMT

Hi Marc -

Since the i.MX6 docs are unclear on this point (4GB on single CS), can you comment on the MMDC register changes that were required moving to 4GB?

Thanks,

Phil