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    <title>i.MX ProcessorsのトピックRe: 8-bit data width DDR3 on iMX6DL</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/8-bit-data-width-DDR3-on-iMX6DL/m-p/485915#M77676</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Steven&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately i.MX6DL does not support 8-bit memory width for MMDC module.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 25 Feb 2016 04:11:14 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-02-25T04:11:14Z</dc:date>
    <item>
      <title>8-bit data width DDR3 on iMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8-bit-data-width-DDR3-on-iMX6DL/m-p/485914#M77675</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have designed a board that uses a single 8Gb (1GB) DDR3 chip (MT41K1G8S-125) and assumed that if you only used x8 you just use the lower dqs0/d[0:7] and it should be fine. However now that I've had the device made, in testing I have found that isn't the case and the 8 most significant bits are lost into the non-existent upper 8-bits for every write to RAM. I've had a look through the reference manual but is there any register settings that I have missed that would allow this device to work, at least for testing purposes while I work on my next design to fix it (Going to change to the MT41K512M16 variant) for future runs.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Feb 2016 00:30:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8-bit-data-width-DDR3-on-iMX6DL/m-p/485914#M77675</guid>
      <dc:creator>stevenbarker</dc:creator>
      <dc:date>2016-02-25T00:30:59Z</dc:date>
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    <item>
      <title>Re: 8-bit data width DDR3 on iMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8-bit-data-width-DDR3-on-iMX6DL/m-p/485915#M77676</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Steven&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately i.MX6DL does not support 8-bit memory width for MMDC module.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Feb 2016 04:11:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8-bit-data-width-DDR3-on-iMX6DL/m-p/485915#M77676</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-02-25T04:11:14Z</dc:date>
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