topic Re: Custom iMX6Q board booting from eMMC 4.41 in i.MX Processors

Custom iMX6Q board booting from eMMC 4.41

robyf — Wed, 03 Feb 2016 14:21:46 GMT

Hi All,

our iMX6Q custom board has the boot selection like below, I've tried to setup booting from eMMC by setting

the switches as "110000110" but the board seems not booing at all from it. I was also not able to boot from microSD

slot so I suspect that the problem is somehow related to wiring below.

The eMMC's PARTITION_CONFIG has been set to boot from boot partition1 where uboot has been dd-ed in to as:

dd if=u-boot-voneus-janas-imx6q.imx of=/dev/mmcblk1boot0 bs=512 seek=2 skip=2

Current eMMC setup is the following:

root@voneus-janas-imx6q:~# mmc extcsd read /dev/mmcblk1

=============================================

Extended CSD rev 1.5 (MMC 4.41)

=============================================

Card Supported Command sets [S_CMD_SET: 0x01]

HPI Features [HPI_FEATURE: 0x03]: implementation based on CMD12

Background operations support [BKOPS_SUPPORT: 0x01]

Background operations status [BKOPS_STATUS: 0x02]

1st Initialisation Time after programmed sector [INI_TIMEOUT_AP: 0xf6]

Power class for 52MHz, DDR at 3.6V [PWR_CL_DDR_52_360: 0x00]

Power class for 52MHz, DDR at 1.95V [PWR_CL_DDR_52_195: 0x00]

Minimum Performance for 8bit at 52MHz in DDR mode:

[MIN_PERF_DDR_W_8_52: 0x00]

[MIN_PERF_DDR_R_8_52: 0x00]

TRIM Multiplier [TRIM_MULT: 0x06]

Secure Feature support [SEC_FEATURE_SUPPORT: 0x15]

Secure Erase Multiplier [SEC_ERASE_MULT: 0x02]

Secure TRIM Multiplier [SEC_TRIM_MULT: 0x03]

Boot Information [BOOT_INFO: 0x07]

Device supports alternative boot method

Device supports dual data rate during boot

Device supports high speed timing during boot

Boot partition size [BOOT_SIZE_MULTI: 0x10]

Access size [ACC_SIZE: 0x06]

High-capacity erase unit size [HC_ERASE_GRP_SIZE: 0x08]

i.e. 4096 KiB

High-capacity erase timeout [ERASE_TIMEOUT_MULT: 0x01]

Reliable write sector count [REL_WR_SEC_C: 0x01]

High-capacity W protect group size [HC_WP_GRP_SIZE: 0x02]

i.e. 8192 KiB

Sleep current (VCC) [S_C_VCC: 0x08]

Sleep current (VCCQ) [S_C_VCCQ: 0x08]

Sleep/awake timeout [S_A_TIMEOUT: 0x10]

Sector Count [SEC_COUNT: 0x00ea0000]

Device is block-addressed

Minimum Write Performance for 8bit:

[MIN_PERF_W_8_52: 0x08]

[MIN_PERF_R_8_52: 0x08]

[MIN_PERF_W_8_26_4_52: 0x08]

[MIN_PERF_R_8_26_4_52: 0x08]

Minimum Write Performance for 4bit:

[MIN_PERF_W_4_26: 0x08]

[MIN_PERF_R_4_26: 0x08]

Power classes registers:

[PWR_CL_26_360: 0x00]

[PWR_CL_52_360: 0x00]

[PWR_CL_26_195: 0x00]

[PWR_CL_52_195: 0x00]

Partition switching timing [PARTITION_SWITCH_TIME: 0x01]

Out-of-interrupt busy timing [OUT_OF_INTERRUPT_TIME: 0x02]

Card Type [CARD_TYPE: 0x07]

HS Dual Data Rate eMMC @52MHz 1.8V or 3VI/O

HS eMMC @52MHz - at rated device voltage(s)

HS eMMC @26MHz - at rated device voltage(s)

CSD structure version [CSD_STRUCTURE: 0x02]

Command set [CMD_SET: 0x00]

Command set revision [CMD_SET_REV: 0x00]

Power class [POWER_CLASS: 0x00]

High-speed interface timing [HS_TIMING: 0x01]

Erased memory content [ERASED_MEM_CONT: 0x00]

Boot configuration bytes [PARTITION_CONFIG: 0x48]

Boot Partition 1 enabled

No access to boot partition

Boot config protection [BOOT_CONFIG_PROT: 0x00]

Boot bus Conditions [BOOT_BUS_CONDITIONS: 0x16]

High-density erase group definition [ERASE_GROUP_DEF: 0x00]

Boot write protection status registers [BOOT_WP_STATUS]: 0x00

Boot Area Write protection [BOOT_WP]: 0x00

Power ro locking: possible

Permanent ro locking: possible

ro lock status: not locked

User area write protection register [USER_WP]: 0x00

FW configuration [FW_CONFIG]: 0x00

RPMB Size [RPMB_SIZE_MULT]: 0x01

Write reliability setting register [WR_REL_SET]: 0x00

user area: existing data is at risk if a power failure occurs during a write operation

partition 1: existing data is at risk if a power failure occurs during a write operation

partition 2: existing data is at risk if a power failure occurs during a write operation

partition 3: existing data is at risk if a power failure occurs during a write operation

partition 4: existing data is at risk if a power failure occurs during a write operation

Write reliability parameter register [WR_REL_PARAM]: 0x05

Device supports writing EXT_CSD_WR_REL_SET

Device supports the enhanced def. of reliable write

Enable background operations handshake [BKOPS_EN]: 0x00

H/W reset function [RST_N_FUNCTION]: 0x00

HPI management [HPI_MGMT]: 0x01

Partitioning Support [PARTITIONING_SUPPORT]: 0x03

Device support partitioning feature

Device can have enhanced tech.

Max Enhanced Area Size [MAX_ENH_SIZE_MULT]: 0x0001d4

i.e. 3833856 KiB

Partitions attribute [PARTITIONS_ATTRIBUTE]: 0x00

Partitioning Setting [PARTITION_SETTING_COMPLETED]: 0x00

Device partition setting NOT complete

General Purpose Partition Size

[GP_SIZE_MULT_4]: 0x000000

[GP_SIZE_MULT_3]: 0x000000

[GP_SIZE_MULT_2]: 0x000000

[GP_SIZE_MULT_1]: 0x000000

Enhanced User Data Area Size [ENH_SIZE_MULT]: 0x000000

i.e. 0 KiB

Enhanced User Data Start Address [ENH_START_ADDR]: 0x000000

i.e. 0 bytes offset

Bad Block Management mode [SEC_BAD_BLK_MGMNT]: 0x00

root@voneus-janas-imx6q:~#

Does anyone notice something wrong?

Cheers,

Roberto Fichera.

Re: Custom iMX6Q board booting from eMMC 4.41

igorpadykov — Thu, 04 Feb 2016 01:40:26 GMT

Hi Roberto

please try to program eMMC with MFG Tool

Programmers (Flash, etc.) (9)

SABRE Board Reference Design|NXP

for booting problems one can attach jtag and check

SRC_SBMR1,2 registers.

Also had you run ddr test ?

i.MX6/7 DDR Stress Test Tool V2.40

uboot should be rebuilt with updated *.cfg data obtained from ddr test

Best regards

igor

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Re: Custom iMX6Q board booting from eMMC 4.41

robyf — Thu, 04 Feb 2016 09:56:47 GMT

Hi Igor,

yeah, the board already passed the DDR test and currently is running with the right calibration values. What is important to know to me is if the dip switches are wired ok, I mean on the PCB. If the eMMC 4.41 (Micron MTFC8GLCDM) configuration looks good to boot up from it. And what are the right fuse values to let the board boot in boot from fuse mode. Basically I would try to boot from fuses to see if there is something wrong in the PCB wiring related to the SD/MMC CFG.

Cheers,

Roberto Fichera.

Re: Custom iMX6Q board booting from eMMC 4.41

igorpadykov — Thu, 04 Feb 2016 10:47:24 GMT

Hi Roberto

one can check if dip switches are right reading SRC_SBMR1,2 registers.

For booting from fuses BT_FUSE_SEL should be blown.

Best regards

igor

Re: Custom iMX6Q board booting from eMMC 4.41

robyf — Thu, 04 Feb 2016 11:01:47 GMT

Hi Igor,

Reading SRC_SBMR1,2 register is ok! I'm currently checking it to see from which device the board booted from. To blow down the fuse correctly I need to know what are the right fuses to boot form my eMMC 4.41 wired to USDHC4. For example something like below would be ok?

BOOT_CFG2[9] = Boot Ack enable/disable?!? Currently in the eMMC is disabled

BOOT_CFG2[12:11] = 11 (uSDHC4)

BOOT_CFG2[15:13] = 110 (8bit DDR eMMC4.4)

and set my dip switches to 00 to boot from uses

or should I need to blow down also BOOT_CFG4[28] = 1 (BT_FUSE_SEL) ?

Cheers,

Roberto Fichera.

Re: Custom iMX6Q board booting from eMMC 4.41

igorpadykov — Thu, 04 Feb 2016 11:28:44 GMT

Hi Roberto

do you have Sabre SD board ? You can boot from eMMC

U512A on spf-27392 schematic, check attached Linux

Guide sect.4.4 How to Boot From eMMC4.4.

Best regards

igor

Re: Custom iMX6Q board booting from eMMC 4.41

robyf — Thu, 04 Feb 2016 11:38:37 GMT

Hi Igor,

I'm using a custom board based on iMX6Q SoC, schematic comes from SabreAI. Software fully based on yocto.

Cheers,

Roberto Fichera.

Re: Custom iMX6Q board booting from eMMC 4.41

athomas — Thu, 04 Feb 2016 21:24:51 GMT

Regardless of your switch/fuse settings, if there is a problem booting from the device the IMX will revert to the serial downloader mode. In that mode, you can use USB OTG and the Manufacturing tool to bootstrap/program the board. Since we boot Linux and the OTG turns into a USB network device, I have used the OTG cable to check how the device enumerated on my computer to suggest if I had a failed boot (if I see a HID device).

Assuming you have used the manufacturing tool to boot the u-boot-voneus-janas-imx6q.imx to make sure it works, you will make sure the boot image is at an offset based on the device type per the table below. From the bootstrapped u-boot, I would also see if I can see the mmc/SD and emmc devices. We boot u-boot from the NAND flash, and I have seen what you describe when I didnt initialize the SPI Flash subsystem properly (and the write presumably failed) and when the image was programmed to the wrong offset. To program the flash we load u-boot.imx into memory at say location 0x10800000 from an SD card using fatload, and then use sf write 0x10800000 0x400 ${filesize}

Table 8-25. Image Vector Table Offset and Initial Load Region Size

Boot Device Type Image Vector Table Offset Initial Load Region Size

NOR 4 Kbyte = 0x1000 bytes Entire Image Size

NAND 1 Kbyte = 0x400 bytes 4 Kbyte

OneNAND 256 bytes = 0x100 bytes 1 Kbyte

SD/MMC/eSD/eMMC/SDXC 1 Kbyte = 0x400 bytes 4 Kbyte

I2C/SPI EEPROM 1 Kbyte = 0x400 bytes 4 Kbyte

SATA 1 Kbyte = 0x400 bytes 4 Kbyte

Re: Custom iMX6Q board booting from eMMC 4.41

robyf — Thu, 04 Feb 2016 22:44:17 GMT

Hi Thomas,

I'm loading uboot, zImage, dtb and initramfs straight in memory via USB OTG using Boundary's imx_usb_loader. After booting the kernel from initramfs I'm setting up the eMMC: partitioning, dd-ing the uboot to boot partition 0 and preparing root fs for first boot. Copying uboot is done by enabling to write the first boot partition and finally

dd if=u-boot-voneus-janas-imx6q.imx of=/dev/mmcblk1boot0 bs=512 seek=2 skip=2

then putting back to read-only the first boot partition and setting up the eMMC via "mmc bootpart" to make visible the partition for booting. All thing thing are done by the linuxrc executed from initramfs.

Cheers,

Roberto Fichera

Re: Custom iMX6Q board booting from eMMC 4.41

igorpadykov — Fri, 05 Feb 2016 01:46:48 GMT

Hi Roberto

regarding imx_usb_loader usage suggest to contact boundary devices support,

it is recommend to use MFG Tools for eMMC programming.

Programmers (Flash, etc.) (9)

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREBRD&fpsp=1&tab=Design_Tools_Tab

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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Re: Custom iMX6Q board booting from eMMC 4.41

athomas — Fri, 05 Feb 2016 12:56:51 GMT

Roberto,

The main points I was trying to make that I think are relevant to your situation are:

1) Regardless of your boot mode/configuration/fuse settings if the device(SD/emmc/flash) cannot be booted from, the imx6 will default back to serial downloader mode. This includes if your boot image on the device is invalid or not at the proper offset. That means your boot settings and schematic MAY be fine, but the imx6 is failing to boot from your desired device.

2) You need to make sure the u-boot.imx image is properly located on the device you have. Looking at your dd command again the bs=512 and seek=2 parameters should properly put the boot.imx at offset 0x400. That said you probably do not want the skip=2 in the your dd command as it will skip the 0x400 of the input file. That said I think you can play around with u-boot build to make that a mute point, but if you are using the same u-boot.imx for boot strapping as you want on the emmc and based on the information you have provided - you probably do not want the skip parameter.

- Aaron

Re: Custom iMX6Q board booting from eMMC 4.41

robyf — Fri, 05 Feb 2016 13:42:23 GMT

Hi Aaron,

This morning I've found exactly what you say at point 2. Basically the skip=2 was causing the problem and now the board is booting correctly from the eMMC.

Cheers,

Roberto Fichera.