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    <title>i.MX Processors中的主题 i.MX6UL</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL/m-p/485179#M77468</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to design a pcb using &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt; i.MX6UL and I am having a huge trouble routing the Address, Command and Controll on the same layer for DDR3. As the rules suggest all of this pins need to be in same layer but is quite difficult. Also I see some designs where it seems they didn't follow this rule. &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt;i.MX6UL development board, DART-6UL. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Is there any reference design that we can follow to route or we should separate the pins between the layers like the reference design from &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt; &lt;/SPAN&gt;&lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt;i.MX6UL development board?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Thanks in advance,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Ricardo F.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 13 Jan 2016 18:17:08 GMT</pubDate>
    <dc:creator>ricardoferreira</dc:creator>
    <dc:date>2016-01-13T18:17:08Z</dc:date>
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      <title>i.MX6UL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL/m-p/485179#M77468</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to design a pcb using &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt; i.MX6UL and I am having a huge trouble routing the Address, Command and Controll on the same layer for DDR3. As the rules suggest all of this pins need to be in same layer but is quite difficult. Also I see some designs where it seems they didn't follow this rule. &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt;i.MX6UL development board, DART-6UL. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Is there any reference design that we can follow to route or we should separate the pins between the layers like the reference design from &lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt; &lt;/SPAN&gt;&lt;SPAN style="color: #505050; font-family: arial, sans-serif; font-size: 14.6667px;"&gt;i.MX6UL development board?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Thanks in advance,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #505050; font-size: 14.6667px; font-family: arial, sans-serif;"&gt;Ricardo F.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Jan 2016 18:17:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL/m-p/485179#M77468</guid>
      <dc:creator>ricardoferreira</dc:creator>
      <dc:date>2016-01-13T18:17:08Z</dc:date>
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    <item>
      <title>Re: i.MX6UL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL/m-p/485180#M77469</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ricardo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am not aware of such design, but routing in different layers allows to minimize crosstalks,&lt;/P&gt;&lt;P&gt;as sect.3.5.8 High speed signal routing recommendations &lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf" title="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf&lt;/A&gt; &lt;/P&gt;&lt;P&gt;suggests:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Clocks or strobes that are on the same layer need at least 2.5x &lt;/P&gt;&lt;P&gt;spacing from an adjacent trace (2.5xheight from reference plane) to reduce cross-talk.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Jan 2016 01:31:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL/m-p/485180#M77469</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-01-14T01:31:53Z</dc:date>
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