<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic i.MX6UL performance issues in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484415#M77302</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;For some reason our test &lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;i.MX6UL board is running slower than older i.MX28. Changing CCM_ANALOG_PLL_ARMn divider increases the performance slightly, but it's still about 3 times slower in integer calculcations.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;What are correct clock register settings for full CPU speed (528MHz). Changing CACRR[ARM_PODF] divider to 0 causes CPU to hang. Is there some specific procedure for changing this bit?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;Using U-Boot from Freescale git and vanilla kernel 4.4.2. U-boot is loaded via serial downloader, then Linux kernel is loaded from SD card and booted. Kernel CPU frequency scaling is disabled.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 24 Feb 2016 11:37:24 GMT</pubDate>
    <dc:creator>jsopenrb</dc:creator>
    <dc:date>2016-02-24T11:37:24Z</dc:date>
    <item>
      <title>i.MX6UL performance issues</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484415#M77302</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;For some reason our test &lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;i.MX6UL board is running slower than older i.MX28. Changing CCM_ANALOG_PLL_ARMn divider increases the performance slightly, but it's still about 3 times slower in integer calculcations.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;What are correct clock register settings for full CPU speed (528MHz). Changing CACRR[ARM_PODF] divider to 0 causes CPU to hang. Is there some specific procedure for changing this bit?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="jive-category-wrap"&gt;&lt;SPAN class="j-catname"&gt;Using U-Boot from Freescale git and vanilla kernel 4.4.2. U-boot is loaded via serial downloader, then Linux kernel is loaded from SD card and booted. Kernel CPU frequency scaling is disabled.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Feb 2016 11:37:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484415#M77302</guid>
      <dc:creator>jsopenrb</dc:creator>
      <dc:date>2016-02-24T11:37:24Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL performance issues</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484416#M77303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi J&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;procedure for setting set cpu frequency to 528 MHz one can find in&lt;/P&gt;&lt;P&gt;AN5170 sect.6.4.4. Video Playback: steps , sect.4.3 Dhrystone benchmark.&lt;/P&gt;&lt;P&gt;cache.freescale.com/files/32bit/doc/app_note/AN5170.pdf&lt;/P&gt;&lt;P&gt;For comparing performance of both processors one can run dhrystone using&lt;/P&gt;&lt;P&gt;arm document DAI0273A_dhrystone_benchmarking.pdf. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Feb 2016 00:35:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484416#M77303</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-02-25T00:35:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL performance issues</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484417#M77304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It turned out that serial downloader boot happens at some lower frequency which is not switched up correctly in u-boot/kernel. Switching boot mode to boot from fuses solves this issue.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 Feb 2016 10:31:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-performance-issues/m-p/484417#M77304</guid>
      <dc:creator>jsopenrb</dc:creator>
      <dc:date>2016-02-29T10:31:03Z</dc:date>
    </item>
  </channel>
</rss>

