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    <title>i.MX ProcessorsのトピックRe: imx6UL ethernet switching performance</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6UL-ethernet-switching-performance/m-p/481123#M76715</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6UL Ethernet controllers offer certain acceleration to the OS&lt;/P&gt;&lt;P&gt;network stack, but these features mostly offload above-L2 tasks, such&lt;/P&gt;&lt;P&gt;as header recognition, checksum calculation, header alignment, etc.&lt;/P&gt;&lt;P&gt;Kernel bridge does not directly interact with these features. &lt;/P&gt;&lt;P&gt;If you wish an ARM-based processor with on-chip L2 switching capabilities,&lt;/P&gt;&lt;P&gt;consider i.MX287. See i.MX28 Reference Manual, Chapter 29 and &lt;/P&gt;&lt;P&gt;i.MX28 EVK Linux Reference Manual, Chapter 16 for more&lt;/P&gt;&lt;P&gt;details.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Platon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 12 Jan 2016 11:19:36 GMT</pubDate>
    <dc:creator>bpe</dc:creator>
    <dc:date>2016-01-12T11:19:36Z</dc:date>
    <item>
      <title>imx6UL ethernet switching performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6UL-ethernet-switching-performance/m-p/481122#M76714</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does i.MX6 Ultralite support any kind of hardware acceleration of Ethernet switching on its two Ethernet interfaces? And if yes how to enable it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I compile and use the Linux Ethernet bridge module, then system load at maximum 100Mbit throughput is approximately 50% when 1500 byte packets are used. If smaller packets are used then the system load goes easily to 100%.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Platform used: IMX6UL-EVK&lt;/P&gt;&lt;P&gt;Part: PCIMX6G2CVM05AA&lt;/P&gt;&lt;P&gt;Kernel/BSP: Linux imx6ulevk 3.14.38-6UL_ga+ge4944a5 (compiled with bridge module)&lt;/P&gt;&lt;P&gt;Traffic generator: iperf -s / iperf -c&lt;/P&gt;&lt;P&gt;Load test: sar -u 5 100&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you very much beforehand.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Vladislav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Jan 2016 12:05:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6UL-ethernet-switching-performance/m-p/481122#M76714</guid>
      <dc:creator>vladislavkasik</dc:creator>
      <dc:date>2016-01-11T12:05:40Z</dc:date>
    </item>
    <item>
      <title>Re: imx6UL ethernet switching performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6UL-ethernet-switching-performance/m-p/481123#M76715</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6UL Ethernet controllers offer certain acceleration to the OS&lt;/P&gt;&lt;P&gt;network stack, but these features mostly offload above-L2 tasks, such&lt;/P&gt;&lt;P&gt;as header recognition, checksum calculation, header alignment, etc.&lt;/P&gt;&lt;P&gt;Kernel bridge does not directly interact with these features. &lt;/P&gt;&lt;P&gt;If you wish an ARM-based processor with on-chip L2 switching capabilities,&lt;/P&gt;&lt;P&gt;consider i.MX287. See i.MX28 Reference Manual, Chapter 29 and &lt;/P&gt;&lt;P&gt;i.MX28 EVK Linux Reference Manual, Chapter 16 for more&lt;/P&gt;&lt;P&gt;details.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Platon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Jan 2016 11:19:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6UL-ethernet-switching-performance/m-p/481123#M76715</guid>
      <dc:creator>bpe</dc:creator>
      <dc:date>2016-01-12T11:19:36Z</dc:date>
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