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    <title>i.MX ProcessorsのトピックRe: Question, i.MX6UL BENAND</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480929#M76670</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; I am afraid, it is impossible to use the NAND as a storage device with its internal ECC.&lt;/P&gt;&lt;P&gt;The reason concerns specific NAND layout, used by GPMI, where &lt;SPAN style="line-height: 1.5;"&gt;512-byte blocks are located &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 1.5;"&gt;with the following spare areas (just after data block). This does not meet layout of the BENAND&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 1.5;"&gt;part; as result ECC area &lt;/SPAN&gt;of BENAND is mixed with data, expected by the GPMI.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; But it would be possible to use the BENAND part if its internal ECC is disabled.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 08 Feb 2016 05:10:29 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-02-08T05:10:29Z</dc:date>
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      <title>Question, i.MX6UL BENAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480926#M76667</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My customer want to use the following Toshiba/BENAND chip with i.MX6UltraLite.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;TC58BVG0S3HTAI0&lt;SPAN style="font-family: 'ＭＳ 明朝',serif;"&gt;（&lt;/SPAN&gt;BENAND&lt;SPAN style="font-family: 'ＭＳ 明朝',serif;"&gt;）&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you check whether the BENAND chip can be used with i.MX6UL?&lt;/P&gt;&lt;P&gt;Please find the attached file for the datasheet of the BENAND.&lt;/P&gt;&lt;P&gt;And please find the another attached file, the BENAND has a restriction on its programming.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Feb 2016 01:03:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480926#M76667</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-02-02T01:03:54Z</dc:date>
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    <item>
      <title>Re: Question, i.MX6UL BENAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480927#M76668</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;TC58BVG0S3HTAI0 has embedded ECC, and&amp;nbsp; I am afraid, it is practically impossible to use &lt;/SPAN&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;"smart" &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;NAND with on-die ECC enabled for boot, since i.MX6 GPMI controller is intended to work with &lt;/SPAN&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;"raw" &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;parts, assuming specific NAND blocks mapping : any NAND is treated as sequence of &lt;/SPAN&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;512-bytes blocks &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;with following spare areas. The ''smart' NANDs use own (different) mapping.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Please look at section 8.5.2.5 (Bad Block Handling in the ROM) of the I.MX6UL RM (IMX6ULRM,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;Rev. 0, 08/2015) for NAND data mapping. As for ECC - section 8.5.2.2 [NAND Flash Boot Flow and &lt;/SPAN&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;Boot &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;Control Blocks&amp;nbsp; (BCB)] describes BCB structures and states about ECC protection, using the &lt;/SPAN&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;internal &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12,0000pt; font-family: Verdana;"&gt;hardware.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;&amp;nbsp;&amp;nbsp; Possible solution – my opinion – applying boot SPI NOR; so that NOR code configures&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana; font-size: 12,0000pt;"&gt;BENAND part to disable its ECC (if possible).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 03 Feb 2016 05:21:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480927#M76668</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-02-03T05:21:52Z</dc:date>
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    <item>
      <title>Re: Question, i.MX6UL BENAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480928#M76669</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your comment.&lt;/P&gt;&lt;P&gt;After boot-up, is it possible to disable ECC function on i.MX6UL by clearing GPMI_ECCCTRL[ENABLE_ECC] bit?&lt;/P&gt;&lt;P&gt;What do you think about the use as storage device, not for boot device?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Feb 2016 08:13:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480928#M76669</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-02-05T08:13:10Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6UL BENAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480929#M76670</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; I am afraid, it is impossible to use the NAND as a storage device with its internal ECC.&lt;/P&gt;&lt;P&gt;The reason concerns specific NAND layout, used by GPMI, where &lt;SPAN style="line-height: 1.5;"&gt;512-byte blocks are located &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 1.5;"&gt;with the following spare areas (just after data block). This does not meet layout of the BENAND&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 1.5;"&gt;part; as result ECC area &lt;/SPAN&gt;of BENAND is mixed with data, expected by the GPMI.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; But it would be possible to use the BENAND part if its internal ECC is disabled.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Feb 2016 05:10:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UL-BENAND/m-p/480929#M76670</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-02-08T05:10:29Z</dc:date>
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