i.MX ProcessorsのトピックRe: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

i.MX6SoloX RGMII1_TX_CTL delay to AR8035

christianpeters — Mon, 01 Feb 2016 09:54:41 GMT

Hi Community,

according to the datasheet of the AR8035 the RGMII1_TX_CTL has to be delayed from . 1.5 to 2ns.

The iMX6SoloX cannot do this. and the integrated delay of the AR8035 is too long with 2,4 nS.

It is not feasible to get the delay by making the track long enough.

Is there easy way to produce the necessary delay?

Thanks a lot.

Christian Peters FAE EBV

Re: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

Yuri — Tue, 02 Feb 2016 02:28:29 GMT

Hello,

The i.MX6SX Datasheet(s) recommend hardware delay (of greater than 1.5 ns and less than 2.0 ns)
for the clock signal. This may be implemented as PCB trace delay or delay scheme. Basically

RGMII specs allow implementation of a delay on TXC or RXC inside the transmitter, but - as we
see -this delay option is not configurable neither for i.MX6SX ENET nor the external PHY.
The Datasheet recommends PCB trace solution.

Have a great day,
Yuri

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Re: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

christianpeters — Thu, 04 Feb 2016 07:57:29 GMT

Dear Yuri,

a pcb trace solution would mean a 260mm trace @ 1,75 nS.

This from layout and EMV point of view, very poor and not feasible.

Any other recommendations?

Thanks for your help.

Christian

Re: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

christianpeters — Thu, 04 Feb 2016 08:53:18 GMT

Hi Juri,

this does not really help as the parts a ECL technology and start at 5$ upwards..

How do NXP realize the delay on the reference board ?

Christian

Re: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

Yuri — Thu, 04 Feb 2016 09:16:32 GMT

The following is i.MX6SX refrence design Summary page :

SABRE Board Reference Design|NXP

Regards,

Yuri.

Re: i.MX6SoloX RGMII1_TX_CTL delay to AR8035

Yuri — Fri, 05 Feb 2016 02:16:12 GMT

Just as an example of implementation

~Yuri.