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    <title>topic Re: Enabling Uarts 4 &amp; 5 on i.MX53 QSB in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180743#M7604</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;maybe there is no clock registered for uart 4/5.&lt;/P&gt;&lt;P&gt;have a look at the mainline kernel - there uart 4/5 are working.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;~matthias&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Nov 2011 07:40:34 GMT</pubDate>
    <dc:creator>MatthiasFend</dc:creator>
    <dc:date>2011-11-02T07:40:34Z</dc:date>
    <item>
      <title>Enabling Uarts 4 &amp; 5 on i.MX53 QSB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180742#M7603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Everyone,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am trying to enable and use Uarts 4 and 5 on i.MX53 QSB&lt;/P&gt;&lt;P&gt;What I did was to add the following code in board-mx53_loco.c:&lt;/P&gt;&lt;P&gt;// for pad initialization&lt;/P&gt;&lt;P&gt;/* UART4 */&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX53_PAD_CSI0_DAT12__UART4_TXD_MUX,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX53_PAD_CSI0_DAT13__UART4_RXD_MUX,&lt;/P&gt;&lt;P&gt;/* UART5 */&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX53_PAD_CSI0_DAT14__UART5_TXD_MUX,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX53_PAD_CSI0_DAT15__UART5_RXD_MUX,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;// for uarts initialization&lt;/P&gt;&lt;P&gt;/* UART4 */&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; imx53_add_imx_uart(3, NULL);&lt;/P&gt;&lt;P&gt;/* UART5 */&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; imx53_add_imx_uart(4, NULL);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But this is what happens at kernel start-up:&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 0.928123] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.010420] Serial: IMX driver&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.010977] imx21-uart.0: ttymxc0 at MMIO 0x53fbc000 (irq = 31) is a IMX&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.744170] console [ttymxc0] enabled&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.760031] imx-uart: probe of imx21-uart.3 failed with error -2&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.766274] imx-uart: probe of imx21-uart.4 failed with error -2&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Uart 1 is OK, other Uarts probing fails:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What I am missing?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks a lot in advance!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 30 Oct 2011 07:25:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180742#M7603</guid>
      <dc:creator>NivelinnPantev</dc:creator>
      <dc:date>2011-10-30T07:25:04Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Uarts 4 &amp; 5 on i.MX53 QSB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180743#M7604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;maybe there is no clock registered for uart 4/5.&lt;/P&gt;&lt;P&gt;have a look at the mainline kernel - there uart 4/5 are working.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;~matthias&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Nov 2011 07:40:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180743#M7604</guid>
      <dc:creator>MatthiasFend</dc:creator>
      <dc:date>2011-11-02T07:40:34Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Uarts 4 &amp; 5 on i.MX53 QSB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180744#M7605</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Matthias,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;And thank you for your help and suggestion!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Well, it has to be latest kernel, it’s &amp;nbsp;3.1.0. from Linaro 11.10 &amp;nbsp;release., Ubuntu Oneiric build&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Nivelinn&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Nov 2011 16:12:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180744#M7605</guid>
      <dc:creator>NivelinnPantev</dc:creator>
      <dc:date>2011-11-02T16:12:51Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Uarts 4 &amp; 5 on i.MX53 QSB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180745#M7606</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi guys,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Found a time to go to the issue:&lt;/P&gt;&lt;P&gt;It is in clock.c, clk_lookup mx53_lookup structure&lt;/P&gt;&lt;P&gt;The following lines:&lt;/P&gt;&lt;P&gt;&amp;nbsp;_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk[0]),&lt;/P&gt;&lt;P&gt;_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk[0]),&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Have to be:&lt;/P&gt;&lt;P&gt;_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk[0]),&lt;/P&gt;&lt;P&gt;_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk[0]),&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now is is shown at start-up:&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.790564] imx21-uart.3: ttymxc3 at MMIO 0x53ff0000 (irq = 13) is a IMX&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.810558] imx21-uart.4: ttymxc4 at MMIO 0x63f90000 (irq = 86) is a IMX&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and&lt;/P&gt;&lt;P&gt;ls /dev/tty*&lt;/P&gt;&lt;P&gt;gives them:&lt;/P&gt;&lt;P&gt;/dev/ttymxc3&lt;/P&gt;&lt;P&gt;/dev/ttymxc4&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Maybe, who ever takes care of mainline kernel support of i.mx53 has to be imformed?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Nov 2011 17:07:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-Uarts-4-5-on-i-MX53-QSB/m-p/180745#M7606</guid>
      <dc:creator>NivelinnPantev</dc:creator>
      <dc:date>2011-11-30T17:07:27Z</dc:date>
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