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    <title>topic issue related to processor selection in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/issue-related-to-processor-selection/m-p/477491#M75777</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, i want to use imx6DL processor in my board and i don't need DDR3 RAM so i am thinking of using asynchronous SRAM. I want to know does 64 bit writes allowed to external SRAM or i have to break iit into two 32 bit writes? My application strongly required 64 bit writes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Jan 2016 05:59:26 GMT</pubDate>
    <dc:creator>samarora</dc:creator>
    <dc:date>2016-01-11T05:59:26Z</dc:date>
    <item>
      <title>issue related to processor selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/issue-related-to-processor-selection/m-p/477491#M75777</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, i want to use imx6DL processor in my board and i don't need DDR3 RAM so i am thinking of using asynchronous SRAM. I want to know does 64 bit writes allowed to external SRAM or i have to break iit into two 32 bit writes? My application strongly required 64 bit writes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Jan 2016 05:59:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/issue-related-to-processor-selection/m-p/477491#M75777</guid>
      <dc:creator>samarora</dc:creator>
      <dc:date>2016-01-11T05:59:26Z</dc:date>
    </item>
    <item>
      <title>Re: issue related to processor selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/issue-related-to-processor-selection/m-p/477492#M75778</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;asynchronous SRAM can be connected to EIM bus i.MX6DL, it has&lt;/P&gt;&lt;P&gt;max. 32 bit width, as shown on Table 40. EIM Internal Module Multiplexing&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf" title="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Jan 2016 10:39:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/issue-related-to-processor-selection/m-p/477492#M75778</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-01-11T10:39:18Z</dc:date>
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