topic DDR Memory Map default config value for TZASC in i.MX Processors

DDR Memory Map default config value for TZASC

myungjinhwang — Mon, 22 Feb 2016 07:12:24 GMT

Dear Freescale team.

I have a i.mx6qsabrelite board.

need to know what is the bellow DDR Memory Map default config for setting TZASC in the board.

becuase there are TZASC1, TZASC2 for MMDC#0, MMDC#1.

the OCOPT_CFG valuses :

OCOTP_CFG0 : 0xDBC90E6A

OCOTP_CFG1 : 0x251191D4

OCOTP_CFG2 : 0x2000008F

OCOTP_CFG3 : 0x00620302

OCOTP_CFG4 : 0x18000030

please help me....

best regards,

mjHwang

Re: DDR Memory Map default config value for TZASC

Yuri — Wed, 24 Feb 2016 09:01:10 GMT

Hello,

The BOOT_CFG3 “DDR Memory Map default config” configures startup

memory configuration. The I.MX6 MMDC supports the following modes :

* 16/32/64-bit DDR3-1066 and LPDDR2-1066 (as single channel, when only MMDC0 is used ) ;

* dual 32-bits LPDDR2 (Fixed 2x32 map) ; channel #1 via MMDC0 and channel #2 via MMDC1 ;

* for LPDDR2 : 2x32 interleaved

The SABRE Lite is equipped with DDR3, and only single channel configuration

is used.

Have a great day,
Yuri

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Re: DDR Memory Map default config value for TZASC

myungjinhwang — Thu, 03 Mar 2016 14:32:17 GMT

Thanks a lot for the reply.

It's really helpful.....

Have a great day.