<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックQuestion, MX13892 XTAL2 routing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-MX13892-XTAL2-routing/m-p/477160#M75688</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My customer found a miss routing of MC13892/XTAL2 which is used with i.MX51 on their custom board.&lt;/P&gt;&lt;P&gt;We received from i.MX community the solution that XTAL2 should be connected to VCOREDIG pin when it is unused.&lt;/P&gt;&lt;P&gt;And the customer wants to know the exact reason why XTAL2 should be connected to VCOREDIG.&lt;/P&gt;&lt;P&gt;Could you give me the answer?&lt;/P&gt;&lt;P&gt;Actually, the rework that the customer connects XTAL2 and VCOREDIG is impossible on their board due to its PCD layout. Do you have any other ideas for the workaround?&lt;/P&gt;&lt;P&gt;The customer thinks that they can pull down XTAL2 to GND, or connect XTAL2 to GND on their board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 04 Apr 2016 01:08:04 GMT</pubDate>
    <dc:creator>Aemj</dc:creator>
    <dc:date>2016-04-04T01:08:04Z</dc:date>
    <item>
      <title>Question, MX13892 XTAL2 routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-MX13892-XTAL2-routing/m-p/477160#M75688</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My customer found a miss routing of MC13892/XTAL2 which is used with i.MX51 on their custom board.&lt;/P&gt;&lt;P&gt;We received from i.MX community the solution that XTAL2 should be connected to VCOREDIG pin when it is unused.&lt;/P&gt;&lt;P&gt;And the customer wants to know the exact reason why XTAL2 should be connected to VCOREDIG.&lt;/P&gt;&lt;P&gt;Could you give me the answer?&lt;/P&gt;&lt;P&gt;Actually, the rework that the customer connects XTAL2 and VCOREDIG is impossible on their board due to its PCD layout. Do you have any other ideas for the workaround?&lt;/P&gt;&lt;P&gt;The customer thinks that they can pull down XTAL2 to GND, or connect XTAL2 to GND on their board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Apr 2016 01:08:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-MX13892-XTAL2-routing/m-p/477160#M75688</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-04-04T01:08:04Z</dc:date>
    </item>
    <item>
      <title>Re: Question, MX13892 XTAL2 routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-MX13892-XTAL2-routing/m-p/477161#M75689</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"If not used, XTAL1 should be connected to ground and XTAL2 to VCOREDIG.&lt;/P&gt;&lt;P style="font-weight: normal; font-style: normal; font-size: 15px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f; text-align: left; text-indent: 0px;"&gt;This is for the internal detector circuit thresholds, there is a circuit which detects&lt;/P&gt;&lt;P&gt;whether a crystal is present or not."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Apr 2016 07:32:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-MX13892-XTAL2-routing/m-p/477161#M75689</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-04-04T07:32:09Z</dc:date>
    </item>
  </channel>
</rss>

