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    <title>i.MX ProcessorsのトピックRe: iMX6DL :  How to reset the PCIe core ?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-How-to-reset-the-PCIe-core/m-p/476728#M75629</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;&amp;nbsp; The "core_rst_n" is internal signal, that may be activated by i.MX6 System Reset Controller (SoC resets). &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;You may look at Chapter 60 [System Reset Controller (SRC)] of the i.MX6 S/DL RM for more details. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;As we can see, there is no separate reset option for the PCIe.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;&amp;nbsp; For PCIe Link establishment You may use bit APP_LTSSM_ENABLE and APP_INIT_RST bits &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;of IOMUXC_GPR12 register.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 18 May 2016 05:35:20 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-05-18T05:35:20Z</dc:date>
    <item>
      <title>iMX6DL :  How to reset the PCIe core ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-How-to-reset-the-PCIe-core/m-p/476727#M75628</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;BR /&gt;I use i.MX6DL PCIe module as a RootComplex.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;After bringing up the PCIe link connected to an endpoint device,&lt;BR /&gt;I want to reset the PCIe core in order to re-bringing up .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope to use the "core_rst_n" signal to reset the PCIe core.&lt;BR /&gt;It is described in Figure 49-9. I/O Interfaces involved in Initialization (IMX6SDLRM)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Question]&lt;BR /&gt;What kind of registers do I need to set up in order to assert&amp;nbsp; "core_rst_n" signal ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Koichi Sakagami &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 May 2016 09:53:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-How-to-reset-the-PCIe-core/m-p/476727#M75628</guid>
      <dc:creator>koichisakagami</dc:creator>
      <dc:date>2016-05-17T09:53:56Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6DL :  How to reset the PCIe core ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-How-to-reset-the-PCIe-core/m-p/476728#M75629</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;&amp;nbsp; The "core_rst_n" is internal signal, that may be activated by i.MX6 System Reset Controller (SoC resets). &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;You may look at Chapter 60 [System Reset Controller (SRC)] of the i.MX6 S/DL RM for more details. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;As we can see, there is no separate reset option for the PCIe.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;&amp;nbsp; For PCIe Link establishment You may use bit APP_LTSSM_ENABLE and APP_INIT_RST bits &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm5 a______"&gt;&lt;SPAN class="tm6"&gt;of IOMUXC_GPR12 register.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 May 2016 05:35:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-How-to-reset-the-PCIe-core/m-p/476728#M75629</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-05-18T05:35:20Z</dc:date>
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