SDMA Event Mapping controlling register bit selection

y_l — Mon, 22 Feb 2016 02:17:20 GMT

For i.MX6 solo/dualite's SDMA event mapping, for instance,

SDMA Event number 23 (ESAI/I2C3) 's description came with muxing description with respect to GPR0[6] IOMUXC register. When dive into IOMUXC_GPR0[6] register, the bit selection for muxing sources is straight and clear.

However, for SDMA Event number 29 (UART3/QSPI1) and 30(UART3.QSPI2), the controlling register (GPR0[21], GPR0[22]) bit selection description are not as clear as what had been described in SDMA event number 23.

Is there's any documentation/information providing insight into IOMUXC_GPR0 register's GPR0[21], GPR0[22] bit field?

Thank you.

~ Y.L

Re: SDMA Event Mapping controlling register bit selection

b36401 — Wed, 16 Mar 2016 09:32:53 GMT

Please refer "SDMA event mapping" chapter of i.MX 6Solo/6DualLite Applications Processor Reference Manual.

We have no more detailed documents. Sorry for the inconvenience.

Have a great day,

Victor

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topic SDMA Event Mapping controlling register bit selection in i.MX Processors

SDMA Event Mapping controlling register bit selection

Re: SDMA Event Mapping controlling register bit selection