<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Sabre Smart Devices RAM Adress Pins</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476149#M75541</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Okay thanks Biyong.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mete&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 29 Jan 2016 11:02:38 GMT</pubDate>
    <dc:creator>atillametetured</dc:creator>
    <dc:date>2016-01-29T11:02:38Z</dc:date>
    <item>
      <title>Sabre Smart Devices RAM Adress Pins</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476145#M75537</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Quick question about the RAM schematioc of Sabre. Oddly, adress pins A15 and A14 are seen as NC pins and on the RAM side they are not connected to the bus but on the imx side they are. Why is it in this matter? Below are the snips from the Sabre Ram schematic;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Memory side;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="RAMQUestion.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/35842i87F70DFCE7320F20/image-size/large?v=v2&amp;amp;px=999" role="button" title="RAMQUestion.PNG" alt="RAMQUestion.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i.MX side;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="RAMQUestion2.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/35893i371F893FD4869C63/image-size/large?v=v2&amp;amp;px=999" role="button" title="RAMQUestion2.PNG" alt="RAMQUestion2.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance and best regards,&lt;/P&gt;&lt;P&gt;Mete&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2016 10:16:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476145#M75537</guid>
      <dc:creator>atillametetured</dc:creator>
      <dc:date>2016-01-29T10:16:26Z</dc:date>
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    <item>
      <title>Re: Sabre Smart Devices RAM Adress Pins</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476146#M75538</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;mt41k128m16jt&amp;nbsp; has three parts with the same package.&lt;/P&gt;&lt;P&gt;The 128Mx16 the row is only&amp;nbsp; [13:0]. It is easy to replace with the another part. Even the part needs row [15:0].&lt;/P&gt;&lt;P&gt;If the i.MX6 side is NC, too. The design has no chance to switch to new part like 256MX8.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Untitled.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/36175i6D380AD4A9E76157/image-size/large?v=v2&amp;amp;px=999" role="button" title="Untitled.png" alt="Untitled.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2016 10:39:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476146#M75538</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2016-01-29T10:39:18Z</dc:date>
    </item>
    <item>
      <title>Re: Sabre Smart Devices RAM Adress Pins</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476147#M75539</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What about 512MX16? Can the design swithc to that? Sorry have a bit hard time udnerstanding the language. So the design implies that Sabre only uses A[13:0] but is designed to fit A[15:0]. Is this what you mean?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2016 10:44:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476147#M75539</guid>
      <dc:creator>atillametetured</dc:creator>
      <dc:date>2016-01-29T10:44:29Z</dc:date>
    </item>
    <item>
      <title>Re: Sabre Smart Devices RAM Adress Pins</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476148#M75540</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, this design can fit row A[15:0].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i.MX6 side row is [15:0] is greater than the DDR device 128Mx16 [13:0]. The [15:14] is not used.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But if we want to use&amp;nbsp; 256MX8. the row is [14:0]. i.MX6 side still can handle cause the A14 is connect.&lt;/P&gt;&lt;P&gt;You just uninstall the device 128Mx16 and install the device 256MX8.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the design on i.MX6 side is like this.&amp;nbsp; A14 and A15 is not connected, then we could not switch the device to 256MX8, because the A14 is really NC.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2016 10:51:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476148#M75540</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2016-01-29T10:51:23Z</dc:date>
    </item>
    <item>
      <title>Re: Sabre Smart Devices RAM Adress Pins</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476149#M75541</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Okay thanks Biyong.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mete&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2016 11:02:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Sabre-Smart-Devices-RAM-Adress-Pins/m-p/476149#M75541</guid>
      <dc:creator>atillametetured</dc:creator>
      <dc:date>2016-01-29T11:02:38Z</dc:date>
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  </channel>
</rss>

