i.mx6 MMDC Core Special Command Register

zc_tee — Fri, 29 Jan 2016 05:59:54 GMT

Hi all,

I am currently fine-tuning my DDR performance, and i come across this MMDC_MDSCR (1Ch offset) register which is used to issue special commands manually towards the external DDR device.

However, the information in the reference manual is not much, and it certainly did not explains the types of special command, and how to use it.

May i know where can i find the information about this Core Special Command? Any explanation on how to set the register, what is the reason and effect on setting the register would be helpful.

Thank you.

Regards,

Tee

Re: i.mx6 MMDC Core Special Command Register

igorpadykov — Fri, 29 Jan 2016 09:52:52 GMT

Hi Tee

this is used for sending special commands to ddr chip, like configuring Mode Registers.

Examples can be found in scripts for ddr tester tool

https://community.freescale.com/docs/DOC-105652

ddr_stress_tester folder ../script/ , for example attached MX6SL_EVK_LPDDR2_512MB_32bit_v0.9.inc:

// LPDDR2 Mode Register Writes

//=============================================================================

setmem /32 0x021b001c =0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration

setmem /32 0x021b001c =0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration

Best regards

igor

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topic Re: i.mx6 MMDC Core Special Command Register in i.MX Processors

i.mx6 MMDC Core Special Command Register

Re: i.mx6 MMDC Core Special Command Register