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    <title>i.MX ProcessorsのトピックRe: [i.mx25] will clock adjusting occur SDRAM memory corruption.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473847#M75028</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Beside, if we do not change the clock, then no memory corruption was found. So, can the clock frequence be adjusted when the SDRAM is working? If not, pls also help share the reason.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;Jianhan Wang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 03 Jun 2016 10:14:54 GMT</pubDate>
    <dc:creator>王剑翰</dc:creator>
    <dc:date>2016-06-03T10:14:54Z</dc:date>
    <item>
      <title>[i.mx25] will clock adjusting occur SDRAM memory corruption.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473846#M75027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US"&gt;Dear,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you help to confirm why does the memory corruption occure after the clock adjusting?&lt;/P&gt;&lt;P&gt;Is there any wrong sequence for below code architecture?&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US"&gt;[Using environment]&lt;BR /&gt; CPU&lt;/SPAN&gt;　&lt;SPAN lang="EN-US"&gt;i.MX25&lt;BR /&gt; SDRAM K4T51163QI-HCE6&lt;BR /&gt; &lt;BR /&gt; [Failure mode]&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Boot1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1. Initialize SDRAM&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2. Change clock: core&amp;nbsp; 133Hz&amp;nbsp; DRAM 66.5Hz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 3. Initialize Nand Flash&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 4. Read bin file of Boot2 from Nand Flash to SDRAM&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 5. Jump to SDRAM， Run Boot2&lt;/P&gt;&lt;P&gt;Boot2&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1. Change ARM CPU mode to Supervisor&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2. Change clock core:&amp;nbsp; 399Hz&amp;nbsp; DRAM 133Hz&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #e23d39;"&gt;&amp;lt;--Memory corruption here（Memory corruption occures on 2 of 40 machines occasionally)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 3. Run library function of IAR, Prepare environment for user main&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;--Program crash for memory corruption.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 4. Run user's main function&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jun 2016 05:24:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473846#M75027</guid>
      <dc:creator>王剑翰</dc:creator>
      <dc:date>2016-06-02T05:24:56Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx25] will clock adjusting occur SDRAM memory corruption.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473847#M75028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Beside, if we do not change the clock, then no memory corruption was found. So, can the clock frequence be adjusted when the SDRAM is working? If not, pls also help share the reason.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;Jianhan Wang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jun 2016 10:14:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473847#M75028</guid>
      <dc:creator>王剑翰</dc:creator>
      <dc:date>2016-06-03T10:14:54Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx25] will clock adjusting occur SDRAM memory corruption.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473848#M75029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Any SDRAM bus frequency change when SDRAM is in operational mode can cause some unpredictable behaviour of the SDRAM. The right sequence of doing this is as follows.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Put SDRAM to Self-Refresh mode.&lt;/P&gt;&lt;P&gt;2. Change the bus frequency.&lt;/P&gt;&lt;P&gt;3. Switch SDRAM back to operational mode.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 12:37:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx25-will-clock-adjusting-occur-SDRAM-memory-corruption/m-p/473848#M75029</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-06-15T12:37:31Z</dc:date>
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