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    <title>i.MX ProcessorsのトピックRe: iMx25 harware register</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470372#M74418</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Simon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this may be related with AIPS priviledge settings,&lt;/P&gt;&lt;P&gt;suggest to create service request for obtaining&lt;/P&gt;&lt;P&gt;AIPS description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 06 Jun 2016 12:30:12 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-06-06T12:30:12Z</dc:date>
    <item>
      <title>iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470369#M74415</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;BR /&gt;I'm running bare metal on iMx25 PDK with debug board. &lt;BR /&gt; I'm trying to access UART register (USR1) on user mode but each time it raise a data abort. &lt;BR /&gt;Is hardware register only accessible from privileged mode ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Documentation says I can read/write as user, may be I miss to configure a register but i don't know which one.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is the exemple code I made to read USR1 at the boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;start_boot:&lt;/P&gt;&lt;P&gt;// After a reset, the mode is ARM, Supervisor, interrupts disabled.&lt;/P&gt;&lt;P&gt;// Invalidate both ICache and DCache : not done upon emulator reset&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r1,=0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; mcr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; p15,0,r1,c7,c7,0&lt;/P&gt;&lt;P&gt;// Disable MMU translation, D cache and enable I cache&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; mrc&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; p15,0,r1,c1,c0,0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r0,=CP_DIS_MASK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // 0xFFFFEFFA&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; and&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r1,r1,r0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; orr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r1,r1,#(1&amp;lt;&amp;lt;12)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; orr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r1,r1,#2&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; mcr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; p15,0,r1,c1,c0,0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;// Initialize clocks&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;/TD&gt;&lt;TD&gt;bl&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD&gt;low_level_init&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;BR /&gt;// Switch to user and try access USR1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; bic&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r0,r0,#MODE_MSK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Clear the mode bits&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; orr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r0,r0,#USR_MODE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set USER mode bits&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; msr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cpsr_c,r0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r3, =0x43f90098&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; r3,[r3]&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you have any idea why I can't access uart register in user mode, any help is welcome.&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Simon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Jun 2016 13:47:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470369#M74415</guid>
      <dc:creator>simonl</dc:creator>
      <dc:date>2016-06-01T13:47:32Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470370#M74416</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Simon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;register may be not accessible when module clock is gated&lt;/P&gt;&lt;P&gt;in CCM, so one can check uart bits in CGCRx registers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jun 2016 00:43:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470370#M74416</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-06-02T00:43:15Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470371#M74417</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor&lt;BR /&gt;I tried with module clock enabled and disabled for my Uart but I have always the same problem.&lt;BR /&gt; When I'm tring to access Uart register in privileged mode, in the same terms it's working. &lt;BR /&gt;I thing I have a permission access problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I check all my config and none register seems to enable a module which manage access permisson. &lt;BR /&gt;So I don't know where problem come from. May be from boot. &lt;BR /&gt;I load my program in RAM direclty with JTAG and configure the iMx25 PDK to boot on SD Card.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Jun 2016 10:08:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470371#M74417</guid>
      <dc:creator>simonl</dc:creator>
      <dc:date>2016-06-06T10:08:10Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470372#M74418</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Simon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this may be related with AIPS priviledge settings,&lt;/P&gt;&lt;P&gt;suggest to create service request for obtaining&lt;/P&gt;&lt;P&gt;AIPS description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Jun 2016 12:30:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470372#M74418</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-06-06T12:30:12Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470373#M74419</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;BR /&gt;Sorry for the wait,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; I didn't found much information about AIPS registers in the iMx25 doc. &lt;BR /&gt;The AIPS A configuration seems to be made by MAX module. &lt;BR /&gt;I looked at my MAX description, but it seems good, all access &lt;SPAN class="short_text" lang="en"&gt;restriction&lt;/SPAN&gt; are disabled ...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Simon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jun 2016 14:08:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470373#M74419</guid>
      <dc:creator>simonl</dc:creator>
      <dc:date>2016-06-13T14:08:52Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470374#M74420</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Simon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;AIPS chapter is not present in RM, you can&lt;/P&gt;&lt;P&gt;obtain it creating service request&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jun 2016 00:44:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470374#M74420</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-06-14T00:44:44Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470375#M74421</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok thank's, I have misunderstood. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jun 2016 06:57:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470375#M74421</guid>
      <dc:creator>simonl</dc:creator>
      <dc:date>2016-06-14T06:57:22Z</dc:date>
    </item>
    <item>
      <title>Re: iMx25 harware register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470376#M74422</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You solve my problem. Thank's a lot igor !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jun 2016 13:36:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMx25-harware-register/m-p/470376#M74422</guid>
      <dc:creator>simonl</dc:creator>
      <dc:date>2016-06-14T13:36:06Z</dc:date>
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