topic Re: What are "primary" and "secondary" about i.MX6DQ MMDC clock duty setting. in i.MX Processors

What are "primary" and "secondary" about i.MX6DQ MMDC clock duty setting.

satoshishimoda — Fri, 11 Mar 2016 08:30:08 GMT

Hi community,

I have a question about i.MX6DQ MMDC.

Please see chapter 44.12.79 in IMX6DQRM (Rev.3).

I want to know what mean "primary" and "secondary" about CK_FTx_DCC field.

Would you let me know that?

Best Regards,

Satoshi Shimoda

Re: What are "primary" and "secondary" about i.MX6DQ MMDC clock duty setting.

Yuri — Mon, 14 Mar 2016 06:24:00 GMT

Hello,

as mentioned in the RM, CK_FT1_DCC is cascaded to CK_FT0_DCC,

so it is possible to get summary duty value.

"The adjustments are cascaded, which means that adjustment FT0 is applied first,

and then adjustment FT1 is applied to the result of the first adjustment. If an adjustment of
3.0% is desired, either stage CK_FT0_DCC or stage CK_FT1_DCC can be used. If a larger

adjustment is desired, then both stages CK_FT0_DCC and CK_FT1_DCC are used, and

applied in the same direction.

Have a great day,
Yuri

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Re: What are "primary" and "secondary" about i.MX6DQ MMDC clock duty setting.

Yuri — Wed, 16 Mar 2016 04:34:23 GMT

Hello,

As for SDCLK Duty Cycle Optimizations, please create request.

How to submit a new question for NXP Support

Regards,

Yuri.