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    <title>topic Re: Drive uSDHC I/O at 1V8 on Linux 3.14.52 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468763#M74056</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; General considerations are as following. The i.MX6 SL has two voltage suppliers : NVCC33_IO and NVCC18_IO. The bit LVE in corresponding Pad Control Register defines what voltage will be applied to the pin. Default value VLE=0 means 3.3V. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; The i.MX6 SL has special recommendations, when using so called low voltage design, in particular it relates to 1.8V SD cards. Please refer to section 7.2.4 (Power-up sequence in low voltage system design) of the “Hardware Development Guide for i.MX 6SoloLite - User Guide”&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;A href="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf" title="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf&lt;/A&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; Also, from the following (internal) thread&amp;nbsp; &lt;A href="https://community.nxp.com/thread/309462"&gt;i.MX6SL : power up sequence for NVCC33_IO&lt;/A&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; In MX6SL, the I/O Gate Keeper circuit is enabled and is powered by NVCC33_IO (LVE bit is "0") by default.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;There is a "potential" issue if the following conditions are matched in customer's design.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1. A MX6SL I/O is connected to external chip with 1.8V powered I/O AND&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2. No 47k ohm (or smaller resistance) pull-low resistor on that I/O &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;If both the above two conditions are matched, the I/O pin voltage may kick-up to ~2V before setting the LVE bit to "1" in U-boot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;Thus the following guidelines should be followed -&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1. Add 47k (or smaller) pull-low resistors on all 1.8V I/Os&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2. Power the external chip 1.8V I/O supply using NVCC18_IO to make sure both MX6SL and external chip I/O supplies would be turned-on at the same time.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;As for Linux support :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;in DTS file, for 1.8V only, please remove no-1-8-v.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; Below is Community thread, where two (hope, useful) patches may be found.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/378904"&gt;How to configure mmc/sdio 1.8v on imx6 linux 3.10.17 BSP&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 25 Apr 2016 05:27:36 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-04-25T05:27:36Z</dc:date>
    <item>
      <title>Drive uSDHC I/O at 1V8 on Linux 3.14.52</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468762#M74055</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;our custom board uses 1V8 IOs for our eMMC (on uSDHC2) and WiFi module (on uSDHC3), around a i.MX6SL.&lt;/P&gt;&lt;P&gt;We just realized that the mmc linux driver on 3.14.52 sets the I/O to 3V3 per default, and only changes it to 1V8 under some very specific circumstances (e.g.; high speed DDR mode). As those circumstances do not apply in our case, the interfaces are being setup to 3V3. (so far, we were relying on setting the I/O levels on the DTS, but had completely missed the fact that VSELECT overrules that)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anybody know of a good and maintainable solution to this ?&lt;/P&gt;&lt;P&gt;Our current plan is to 'hack' the driver to force it to do the right thing, but that is always problematic when upgrading kernels and the like.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have observed that kernel 3.16 (in core/mmc.c power_up()) adds some extra code that attempts to automatic select the right voltage based on the restrictions of the 'regulator' , but I haven't managed to get a viable solution for defining the regulator in the dts that has the behaviour ? (anybody had any advise on that).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Raul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Apr 2016 13:05:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468762#M74055</guid>
      <dc:creator>raulbenetballes</dc:creator>
      <dc:date>2016-04-22T13:05:37Z</dc:date>
    </item>
    <item>
      <title>Re: Drive uSDHC I/O at 1V8 on Linux 3.14.52</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468763#M74056</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; General considerations are as following. The i.MX6 SL has two voltage suppliers : NVCC33_IO and NVCC18_IO. The bit LVE in corresponding Pad Control Register defines what voltage will be applied to the pin. Default value VLE=0 means 3.3V. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; The i.MX6 SL has special recommendations, when using so called low voltage design, in particular it relates to 1.8V SD cards. Please refer to section 7.2.4 (Power-up sequence in low voltage system design) of the “Hardware Development Guide for i.MX 6SoloLite - User Guide”&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;A href="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf" title="http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf&lt;/A&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; Also, from the following (internal) thread&amp;nbsp; &lt;A href="https://community.nxp.com/thread/309462"&gt;i.MX6SL : power up sequence for NVCC33_IO&lt;/A&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; In MX6SL, the I/O Gate Keeper circuit is enabled and is powered by NVCC33_IO (LVE bit is "0") by default.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;There is a "potential" issue if the following conditions are matched in customer's design.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1. A MX6SL I/O is connected to external chip with 1.8V powered I/O AND&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2. No 47k ohm (or smaller resistance) pull-low resistor on that I/O &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;If both the above two conditions are matched, the I/O pin voltage may kick-up to ~2V before setting the LVE bit to "1" in U-boot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;Thus the following guidelines should be followed -&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1. Add 47k (or smaller) pull-low resistors on all 1.8V I/Os&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2. Power the external chip 1.8V I/O supply using NVCC18_IO to make sure both MX6SL and external chip I/O supplies would be turned-on at the same time.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;As for Linux support :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;in DTS file, for 1.8V only, please remove no-1-8-v.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm5"&gt;&amp;nbsp; Below is Community thread, where two (hope, useful) patches may be found.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/378904"&gt;How to configure mmc/sdio 1.8v on imx6 linux 3.10.17 BSP&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Apr 2016 05:27:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468763#M74056</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-04-25T05:27:36Z</dc:date>
    </item>
    <item>
      <title>Re: Drive uSDHC I/O at 1V8 on Linux 3.14.52</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468764#M74057</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in the i.MX6SL changing the value of the VSELECT bit of register uSDHCx_VEND_SPEC, changes the I/O voltage of that particular uSDHCx interface, regardless of the LV setting.&lt;/P&gt;&lt;P&gt;This is not clear in the documentation, but I have found out by writting to it.&lt;/P&gt;&lt;P&gt;If I write 1, then SD_CLK goes to 1.8V. (SD_CLK is the only signal I can probe in my design with oscilloscope)&lt;/P&gt;&lt;P&gt;If I write 0, then SD_CLK goes to 3.3V.&lt;/P&gt;&lt;P&gt;That is whilst LV=1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is consistent with the SD Driver code in the Linux Kernel. Depending on the selected voltage rail, it sets the VSELECT accordignly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My issue is that the driver on 3.14.52 has no provision for driving the eMMC at 1.8V _all_the_time_.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Raul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Apr 2016 11:16:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468764#M74057</guid>
      <dc:creator>raulbenetballes</dc:creator>
      <dc:date>2016-04-25T11:16:26Z</dc:date>
    </item>
    <item>
      <title>Re: Drive uSDHC I/O at 1V8 on Linux 3.14.52</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468765#M74058</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; yes, "&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;If a pin is set to a uSDHC mode in the MUXCTL register, then the LVE field of the PAD Settings &lt;BR /&gt;register is ignored. The single register field that controls the voltage settings for the i.MX6SL processor &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;pads and the external card pads is the VSELECT field in register uSDHCx_VEND_SPEC.&lt;/SPAN&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 May 2016 05:11:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Drive-uSDHC-I-O-at-1V8-on-Linux-3-14-52/m-p/468765#M74058</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-05-13T05:11:04Z</dc:date>
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