topic Re: Unexpected UART_RTS_B interrupt on i.MX6UL in i.MX Processors

Unexpected UART_RTS_B interrupt on i.MX6UL

yuuki — Thu, 18 Feb 2016 14:12:27 GMT

Dear all,

We have a problem that RTS_B interrupt occurs though UART6 is not used.

CPU is i.MX6UL.

BSP is L3.14.52_1.1.0-ga

In IOMUX, the UART6_RTS_B signal is assigned to CSI_VSYNC pin(ALT8) and ENET1_TX_EN pin(ALT1).

However, CSI_VSYNC pin is used as ALT1:USDHC2_CLK and ENET_TX_EN pin is used as ALT0:ENET_TX_EN.

- IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN 0x020E00D8 0x00000000

- IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC 0x020E01DC 0x00000001

When a clock is input into CSI_VSINC pin, an interrupt of UART_RTS_B occurs.

It seems that a signal from CSI_VSYNC pin is entered in RTS of UART port.

IOMUXC_UART6_RTS_B_SELECT_INPUT register remains a default value

(0x00000000 :CSI_VSYNC_ALT8 => UART6_RTS_B)

Would you tell me the method to disable RTS_B interrupt?

Best Regards,

Yuuki

Re: Unexpected UART_RTS_B interrupt on i.MX6UL

gusarambula — Thu, 25 Feb 2016 21:48:46 GMT

Hello Yuuki,

Are you still having this issue?

I would recommend looking for more instances on the Device Tree where there could be a conflict on the function of the pin. Especially make sure that the UART module status is set to disable since it won’t be used.

Regards,

Re: Unexpected UART_RTS_B interrupt on i.MX6UL

yuuki — Wed, 02 Mar 2016 06:55:38 GMT

Dear gusarambula-san,

Thank you for your response.

We still have this problem

I'm sorry, We use UART6. However, We do not use RTS and CTS function.

Now, the RTSDEN bit of the UART6_UCR1 register is set in "1: RTS Delta Interrupt Enable".

In Linux BSP "drivers/tty/serial/imx.c" , this is set by default. (We do not make any modifications.)

According to the explanation of RTSDEN bit, "The current status of the RTS_B pin is read in the RTSS bit."

When the register setting related to the RTS_B pin is as follows,

Is a status of CSI_VSYNC pin read as a RTS_B status ?

- The IOMUXC_UART6_RTS_B_SELECT_INPUT register is a default state, too

00:CSI_VSYNC_ALT8

- And, the IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC register is set in ALT1:USDHC_CLK

The CSI_VSYNC pad is assigned to USDHC_CLK.

In order to avoid unexpected UART_RTS_B interrupt, should RTSDEN bit be set to Disable?

May I have advice?

Best Regards,

Yuuki

Re: Unexpected UART_RTS_B interrupt on i.MX6UL

gusarambula — Tue, 15 Mar 2016 18:32:33 GMT

Hello Yuuki,

My apologized for the delay. Internal architecture do require you to disable the RTSDEN bit in order to avoid an interrupt input on this pin.

Regards,