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    <title>topic Re: Question, i.MX25 KPP port usage in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466049#M73412</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Fabio,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your reply but I need more detailed explanation on that.&lt;/P&gt;&lt;P&gt;I think the port, KPP_ROW6, can be configured as an output port by configuring Keypad Data Direction Register (KDDR).&lt;/P&gt;&lt;P&gt;And I think one can control the output level of KPP_ROW6 by writing 1 or 0 bit into KPDR[6].&lt;/P&gt;&lt;P&gt;Am I wrong?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 06 Jan 2016 01:40:17 GMT</pubDate>
    <dc:creator>Aemj</dc:creator>
    <dc:date>2016-01-06T01:40:17Z</dc:date>
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      <title>Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466047#M73410</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to ask about KPP port of i.MX25.&lt;/P&gt;&lt;P&gt;My customer plans to use KPP_ROW6(V5 pin) port of i.MX257 as a GPIO output.&lt;/P&gt;&lt;P&gt;The customer believes that the KPP_ROW6 pin can be used to output High or Low at any desired timing.&lt;/P&gt;&lt;P&gt;Is it true?&lt;/P&gt;&lt;P&gt;Please let me know if you have any concern on that.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Jan 2016 11:15:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466047#M73410</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-01-05T11:15:10Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466048#M73411</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;There is no GPIO functionality associated with this particular pin.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Fabio Estevam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Jan 2016 13:14:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466048#M73411</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2016-01-05T13:14:18Z</dc:date>
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      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466049#M73412</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Fabio,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your reply but I need more detailed explanation on that.&lt;/P&gt;&lt;P&gt;I think the port, KPP_ROW6, can be configured as an output port by configuring Keypad Data Direction Register (KDDR).&lt;/P&gt;&lt;P&gt;And I think one can control the output level of KPP_ROW6 by writing 1 or 0 bit into KPDR[6].&lt;/P&gt;&lt;P&gt;Am I wrong?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Jan 2016 01:40:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466049#M73412</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-01-06T01:40:17Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466050#M73413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; KPP_ROW6 (V5) pin has no GPIO functionality as Fabio mentioned. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Nevertheless, You are right, the KPP in itself allows to control pin state. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;KPCR[KRE6] = 0 (Row is not included in the keypad key press detect)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;KDDR[KRDD6] = 1 (ROW pin configured as an output) &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;KPDR[KRD6] = 1/0 (data)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Jan 2016 07:44:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466050#M73413</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-01-06T07:44:57Z</dc:date>
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    <item>
      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466051#M73414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The reference manual of i.MX25 says as below.&lt;/P&gt;&lt;P&gt;"The kKeypad port (KPP) is a 16-bit peripheral that can be used as a keypad matrix interface or as general&lt;/P&gt;&lt;P&gt;purpose input/output (I/O)."&lt;/P&gt;&lt;P&gt;Could you give your detailed reason why you say that KPP_ROW6 (V5) pin has no GPIO functionality?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Jan 2016 09:09:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466051#M73414</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-01-06T09:09:43Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466052#M73415</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Now I see the response from Yuri and understood that it is possible to program the KPP interface to use the pin as an output.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sorry for the confusion.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Fabio Estevam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Jan 2016 10:02:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466052#M73415</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2016-01-06T10:02:18Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX25 KPP port usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466053#M73416</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; &lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt; why you say that KPP_ROW6 (V5) pin has no GPIO functionality?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Most of KPP signals can be configured as GPIO via IOMUXC_SW_MUX_CTL_PAD_KPP-...&lt;/P&gt;&lt;P&gt;registers, but the KPP_ROW6 does not have corresponding register.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; Only the following ones are available :&amp;nbsp; &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_ROW0 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_ROW1 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_ROW2 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_ROW3 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_COL0 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_COL1 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_COL2 &lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_KPP_COL3&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Jan 2016 04:35:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX25-KPP-port-usage/m-p/466053#M73416</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-01-14T04:35:39Z</dc:date>
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