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    <title>i.MX ProcessorsのトピックRe: question about pcie</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464825#M73177</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;a) Please refer to the Chapter 40 of the attached document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;b) There is no EP functionality implementation in the current Linux BSP driver.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 22 Apr 2016 05:28:14 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2016-04-22T05:28:14Z</dc:date>
    <item>
      <title>question about pcie</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464824#M73176</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm testing PCIe with SABRE lite board. there are some questions about PCIe.&lt;/P&gt;&lt;P&gt;a) In chapter memory map of IMX6DQRM, it assigns a range of address as follows.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Start address&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; End address&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Size&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Description&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 01FF_C000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 01FF_FFFF&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16KB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PCIe register&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0100_0000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 01FF_BFFF&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16368KB&amp;nbsp; PCIe&lt;/P&gt;&lt;P&gt;I want to know the usage of the 16368KB space. Is PCIe BAR must mapped to this memory space? And is the size of BAR space must less than 16368KB?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;b) I have had my board work in RC mode. How can I set PCIe working in EP mode?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Apr 2016 05:24:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464824#M73176</guid>
      <dc:creator>ainolike</dc:creator>
      <dc:date>2016-04-21T05:24:06Z</dc:date>
    </item>
    <item>
      <title>Re: question about pcie</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464825#M73177</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;a) Please refer to the Chapter 40 of the attached document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;b) There is no EP functionality implementation in the current Linux BSP driver.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Apr 2016 05:28:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464825#M73177</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-04-22T05:28:14Z</dc:date>
    </item>
    <item>
      <title>Re: question about pcie</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464826#M73178</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; as for PCIe EP mode - perhaps the following helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/386833"&gt;Configuring the kernel for RC/EP communication&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Apr 2016 07:20:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-pcie/m-p/464826#M73178</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-04-22T07:20:31Z</dc:date>
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