topic Re: maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/maximum-delay-between-the-write-into-the-ECSPIx-CONFIGREG/m-p/464598#M73126 <HTML><HEAD></HEAD><BODY><P>You are right in that the maximum delay between writing to the ECSPIx_CONFIGREG register that changes some SCLK parameters (e.g. SCLK polarity or SCLK idle state) and actual parameter change is one SCLK clock period.</P><P><BR />Have a great day,<BR />Artur</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Thu, 21 Apr 2016 10:29:13 GMT art 2016-04-21T10:29:13Z maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity https://community.nxp.com/t5/i-MX-Processors/maximum-delay-between-the-write-into-the-ECSPIx-CONFIGREG/m-p/464597#M73125 <HTML><HEAD></HEAD><BODY><P>Dear all,</P><P></P><P>We are porting of Linux to our i.MX6 solo board to a base in Linux L3.10.53 BSP.</P><P>In our system, Flash and RTC are connected to SPI.</P><P></P><P>The device connected to SSx of SPI is the following.<BR />SS0: Flash 200MHz<BR />SS1: Flash 200MHz<BR />SS2: RTC 20MHz</P><P></P><P>With switches from SS2 to SS0, we found SCLK polarity changing after GPIO chipselect was asserted.</P><P>We found the following patch about SPI.</P><P><A href="http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=6fd8b8503a0dcf66510314dc054745087ae89f94">http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=6fd8b8503a0dcf66510314dc054745087ae89f94</A></P><P></P><P>The contents of this patch are included in Linux L3 .10.53 BSP.<BR />However, this problem does not seem to be solved.</P><P></P><P>According to Explanation of this patch, the following is explained.<BR />"Therefore, the time it takes for the write to ECSPIx_CONFIGREG to take effect in the hardware is up to the duration of 1 tick of the SCLK clock."</P><P></P><P>For i.MX6, it seems that the delay time is bigger than 1 tick of the SCLK clock.</P><P></P><P>Would you tell me the maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity?</P><P></P><P></P><P></P><P>It it is the setting that SCLK polarity is not changed, a glitch occurs on SCLK.<BR /><A _jive_internal="true" href="https://community.nxp.com/thread/386935">https://community.freescale.com/thread/386935</A></P><P></P><P>Best Regards,<BR />Yuuki</P></BODY></HTML> Thu, 21 Apr 2016 03:09:06 GMT https://community.nxp.com/t5/i-MX-Processors/maximum-delay-between-the-write-into-the-ECSPIx-CONFIGREG/m-p/464597#M73125 yuuki 2016-04-21T03:09:06Z Re: maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity https://community.nxp.com/t5/i-MX-Processors/maximum-delay-between-the-write-into-the-ECSPIx-CONFIGREG/m-p/464598#M73126 <HTML><HEAD></HEAD><BODY><P>You are right in that the maximum delay between writing to the ECSPIx_CONFIGREG register that changes some SCLK parameters (e.g. SCLK polarity or SCLK idle state) and actual parameter change is one SCLK clock period.</P><P><BR />Have a great day,<BR />Artur</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Thu, 21 Apr 2016 10:29:13 GMT https://community.nxp.com/t5/i-MX-Processors/maximum-delay-between-the-write-into-the-ECSPIx-CONFIGREG/m-p/464598#M73126 art 2016-04-21T10:29:13Z