<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: 6UL Simplified power design ?  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/6UL-Simplified-power-design/m-p/464219#M73008</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi SJA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes seems this is possible, also power-up sequence should be&lt;/P&gt;&lt;P&gt;observed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 31 May 2016 00:54:31 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-05-31T00:54:31Z</dc:date>
    <item>
      <title>6UL Simplified power design ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/6UL-Simplified-power-design/m-p/464218#M73007</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have a design with no need for any power saving modes.&lt;/P&gt;&lt;P&gt;Can we use a simplified power design with two rails 3.3v and 1.35v ?&lt;/P&gt;&lt;P&gt;1.35v would feed VDD_SOC_IN and NVCC_DRAM (and DRAM VCC)&lt;/P&gt;&lt;P&gt;3.3v would feed VDD_HIGH_IN, VDD_SNVS_IN and the other NVCC peripheral rails.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 May 2016 21:24:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/6UL-Simplified-power-design/m-p/464218#M73007</guid>
      <dc:creator>SJA</dc:creator>
      <dc:date>2016-05-30T21:24:36Z</dc:date>
    </item>
    <item>
      <title>Re: 6UL Simplified power design ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/6UL-Simplified-power-design/m-p/464219#M73008</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi SJA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes seems this is possible, also power-up sequence should be&lt;/P&gt;&lt;P&gt;observed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 May 2016 00:54:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/6UL-Simplified-power-design/m-p/464219#M73008</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-05-31T00:54:31Z</dc:date>
    </item>
  </channel>
</rss>

