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    <title>topic Re: imx6 enet in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464115#M72996</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi dong&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for &lt;SPAN style="font-size: 12pt;"&gt;DMA_CLASS_EN &lt;/SPAN&gt;description please check &lt;/P&gt;&lt;P&gt;sect.24.5.42 DMA Class Based Configuration (ENETx_DMAnCFG) i.MX6SX Reference Manual &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX6SXRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 21 Apr 2016 00:22:21 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-04-21T00:22:21Z</dc:date>
    <item>
      <title>imx6 enet</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464114#M72995</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to i.MX 6 SD Applications Processor reference&amp;nbsp; manual, &lt;/P&gt;&lt;P data-canvas-width="564.4099999999999" style="font-size: 23.3333px; font-family: serif;"&gt;&lt;SPAN style="font-size: 12pt;"&gt;Legacy buffer descriptors are used only in single-ring mode,&lt;/SPAN&gt;&lt;/P&gt;&lt;P data-canvas-width="178.8733333333333" style="font-family: serif;"&gt;&lt;SPAN style="font-size: 12pt;"&gt;that is, when DMAnCFG[DMA_CLASS_EN] are zero.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;but I cannot find this register, so when descriptors reach the last one, they cannot warp back, errors happen.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Apr 2016 14:44:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464114#M72995</guid>
      <dc:creator>dongfangxiu</dc:creator>
      <dc:date>2016-04-20T14:44:46Z</dc:date>
    </item>
    <item>
      <title>Re: imx6 enet</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464115#M72996</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi dong&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for &lt;SPAN style="font-size: 12pt;"&gt;DMA_CLASS_EN &lt;/SPAN&gt;description please check &lt;/P&gt;&lt;P&gt;sect.24.5.42 DMA Class Based Configuration (ENETx_DMAnCFG) i.MX6SX Reference Manual &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX6SXRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Apr 2016 00:22:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464115#M72996</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-04-21T00:22:21Z</dc:date>
    </item>
    <item>
      <title>Re: imx6 enet</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464116#M72997</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks! It comes out my cache has some problem. Another problem is, when I ping my PC with 10000 bytes packets, the link will down sometimes. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Apr 2016 05:37:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-enet/m-p/464116#M72997</guid>
      <dc:creator>dongfangxiu</dc:creator>
      <dc:date>2016-04-21T05:37:33Z</dc:date>
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