ODT setting

sparkyee — Wed, 11 May 2016 18:42:49 GMT

Hi,

I have successfully finished SI and timing closure using Hyperlynx 9.3 simulation tool. The tool requires

me to enable (ddr3_odt_t60_sel11_mi) ODT settings for read accesses from the memory to the MMDC controller. I want to know if this is accomplished in the MPODTCTRL register (0x021B01818) or in a IOMUX_SW_PAD_CTL_PAD_DRAM_xxxx register? Also in the Programming AID Ver 1.9 the MPODTCTRL register seems to have ODT disabled for READ accesses since the lower 4 bits are set to "7"? I have read all of the ODT threads here and there seems to be a lot confusion about setting ODT properly. I have used Hyperlynx on iMX31 and

iMX53 designs before and have had excellent correlation to the physical design. I want to make sure I translate the simulation output into correct register settings in the initialization code. My design emulates the Sabre SD board but

was laid out in Expedition instead or Cadence allegro. Thanks for your help!

Re: ODT setting

igorpadykov — Thu, 12 May 2016 00:26:11 GMT

Hi Larry

ODT settings of IOMUX are for the DDR Address and control pins,

and the ODT settings of MMDCx_MPODTCTRL are for the Data bus (by byte group).

So you can controls the ODT value for each byte group by the ODTx_INT_RES.

Best regards

igor

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topic Re: ODT setting in i.MX Processors

ODT setting

Re: ODT setting