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    <title>topic Re: Query on i.MX6Q IBIS model in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Query-on-i-MX6Q-IBIS-model/m-p/460512#M72251</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Anand&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;some pins are not covered by ibis model, as described in Table 9-6. i.MX6 pins not supported by IBIS&lt;/P&gt;&lt;P&gt;i.MX6 System Development User’s Guide &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FIMX6DQ6SDLHDG.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 30 May 2016 00:34:03 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-05-30T00:34:03Z</dc:date>
    <item>
      <title>Query on i.MX6Q IBIS model</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Query-on-i-MX6Q-IBIS-model/m-p/460511#M72250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Hi&lt;/P&gt;&lt;P&gt;I have downloaded the IBIS model for i.MX6Q and I want to simulate for SATA, PCIe signals. I am Observing that the SATA and PCIe TX diff pairs are assigned as inputs. In this case how can I use the i.Mx6q as driver to transmit the bit pattern&lt;/P&gt;&lt;P&gt;Could you please clarify on this &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &lt;/P&gt;&lt;P&gt;Anand M&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 29 May 2016 07:16:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Query-on-i-MX6Q-IBIS-model/m-p/460511#M72250</guid>
      <dc:creator>anandmeharwade</dc:creator>
      <dc:date>2016-05-29T07:16:20Z</dc:date>
    </item>
    <item>
      <title>Re: Query on i.MX6Q IBIS model</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Query-on-i-MX6Q-IBIS-model/m-p/460512#M72251</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Anand&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;some pins are not covered by ibis model, as described in Table 9-6. i.MX6 pins not supported by IBIS&lt;/P&gt;&lt;P&gt;i.MX6 System Development User’s Guide &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FIMX6DQ6SDLHDG.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 May 2016 00:34:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Query-on-i-MX6Q-IBIS-model/m-p/460512#M72251</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-05-30T00:34:03Z</dc:date>
    </item>
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