i.MX6Solo:UART DMA transfer problem

koichisakagami — Fri, 06 Nov 2015 02:33:48 GMT

Dear community,

We have been developing our product with iMX6Solo.

[Background]
When we use the UART DMA transfer with "RXTL=8 CTSTL=8", it works fine.
However, when we use the UART DMA transfer with "RXTL=16 CTSTL=16",unnecessary data are included in RX data.

The unnecessary data are not included in the real waveform.
The appearance frequency of unnecessary data is high-frequency.
The unnecessary data appear 8 byte order.

[Question]
We changed only " RXTL and CTSTL field".

Why are the unnecessary data included in RX data ?
Do we have to set any register other than RXTL and CTSTL in order to work uart module correctly ?

We attached log file. (Red character is unnecessary data.)
Could you check it and advise us ?

[ 52.059266] [bt] open ttymxc1

[ 52.059284] [bt] UCR1 = 0x00000021

[ 52.059294] [bt] UCR2 = 0x00000007

[ 52.059303] [bt] UCR3 = 0x00000784

[ 52.059311] [bt] UCR4 = 0x00004000

[ 52.059358] [bt] set ttymxc1 speed: 9600

[ 52.059368] [bt] UCR1 = 0x00000d2d

[ 52.059376] [bt] UCR2 = 0x00004027

[ 52.059383] [bt] UCR3 = 0x00000784

[ 52.059391] [bt] UCR4 = 0x00004040

[ 52.059628] [bt] set ttymxc1 speed: 9600

[ 52.059641] [bt] UCR1 = 0x00000d2d

[ 52.059650] [bt] UCR2 = 0x00002027

[ 52.059658] [bt] UCR3 = 0x00000784

[ 52.059665] [bt] UCR4 = 0x00004040

[ 52.059721] [bt] set ttymxc1 speed: 115200

[ 52.059731] [bt] UCR1 = 0x00000d2d

[ 52.059739] [bt] UCR2 = 0x00002027

[ 52.059746] [bt] UCR3 = 0x00000784

[ 52.059754] [bt] UCR4 = 0x00004040

[ 52.237021] [bt] USR1 = 0x00006040

[ 52.237031] [bt] USR2 = 0x00004008

[ 52.237043] [bt] rx: 04 0E 04 04 03 0C 00

[ 52.237049] [bt] USR1 = 0x00006040

[ 52.237053] [bt] USR2 = 0x00004008

[ 52.268972] [bt] rx: 04 0E 0B 04 05 10 00 FD 00 00 00 00 00 00 00 00 03 FE 04 00

[ 52.268980] [bt] rx: 03 00

[ 52.268988] [bt] USR1 = 0x00006040

[ 52.268992] [bt] USR2 = 0x00004008

[ 52.309350] [bt] rx: 04 0E 04 04 33 0C 01

[ 52.309370] [bt] USR1 = 0x00006040

[ 52.309379] [bt] USR2 = 0x00004008

[ 52.338923] [bt] rx: 04 0E 0C 04 03 10 00 FF 03 03 03 03 03 03 03 03 FB AD FE DB

[ 52.338933] [bt] rx: FF 7B 87

[ 52.338942] [bt] USR1 = 0x00006040

[ 52.338946] [bt] USR2 = 0x00004008

[ 52.368318] [bt] rx: 04 0E 0E 04 04 10 00 01 03 03 03 03 03 03 03 03 01 00 00 00

[ 52.368328] [bt] rx: 00 00 00 00 01 01 01 01 01 01 01 01 00

[ 52.368336] [bt] USR1 = 0x00006040

[ 52.368340] [bt] USR2 = 0x00004008

Best Regards,
Koichi Sakagami

Re: i.MX6Solo:UART DMA transfer problem

igorpadykov — Tue, 24 Nov 2015 00:57:11 GMT

Hi Koichi

In general this may be caused by fact that sdma script watermark level

also should be changed when RXTL changed. Please note that

FSL provides BSPs with thoroughly tested sdma scripts and

drivers which use these scripts. Sorry, FSL does not support

modifications and customizations sdma scripts and drivers using them.

If you have special reasons for that please elevate this through local marketing.

Best regards

igor

Re: i.MX6Solo:UART DMA transfer problem

koichisakagami — Tue, 24 Nov 2015 01:03:51 GMT

Dear Igor san,

Thank you for your advice.

We will check them.

Best regards

Sakagami

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i.MX6Solo:UART DMA transfer problem

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Re: i.MX6Solo:UART DMA transfer problem