topic Re: iMX6q pcie interface with Xilinx device in i.MX Processors

iMX6q pcie interface with Xilinx device

sumeetdube — Sat, 22 Aug 2015 05:54:23 GMT

We have a problem interfacing a Xiinx Spartan-6 FPGA to pcie port of iMX6q on our custom board.

We can detect the device using pci-utils command lspci but cannot read/write access to the device using mmap() (we used memtool)

We get the following error,

Reading 0x1 count starting at add[ 347.307257] Unhandled fault: external abort on non-linefetch (0x1018) at 0x76f3b000
address 0x01300000

Bus error

We think this is beacuse the memory is not defined in /proc/iomem.

Do we need to write a driver for the device even if it is detected .

And how to assign this memory region in the pcie attribute in devicetree.

Currently the pcie part looks like this,

pcie: pcie@0x01000000 {

compatible = "fsl,imx6q-pcie", "snps,dw-pcie";

reg = <0x01ffc000 0x4000>; /* DBI */

#address-cells = <3>;

#size-cells = <2>;

device_type = "pci";

ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */

0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */

0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */

num-lanes = <1>;

interrupts = <0 123 0x04>;

clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>;

clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate";

status = "okay";

};

I have attached lspci verbose output , /proc/iomem output and the error.

We think it has something to do with the ranges filed but cannot fully understand how to change for our device.

Original Attachment has been moved to: error.log.zip

Original Attachment has been moved to: iomem.zip

Original Attachment has been moved to: lspci_verbose.log.zip

Original Attachment has been moved to: lspci.log.zip

Re: iMX6q pcie interface with Xilinx device

igorpadykov — Mon, 24 Aug 2015 03:56:35 GMT

Hi Sumeet

for understanding PCIe one can look at example below

describing emulation the pcie ep as ram device

i.MX6Q PCIe EP/RC Validation System

Best regards

igor

Re: iMX6q pcie interface with Xilinx device

sumeetdube — Mon, 24 Aug 2015 06:52:13 GMT

Yes i read that post,

I also enabled RC support according to the post.

CONFIG_IMX_PCIE=y

# CONFIG_IMX_PCIE_EP_MODE_IN_EP_RC_SYS is not set

CONFIG_IMX_PCIE_RC_MODE_IN_EP_RC_SYS=y

But i am not able to apply the patch (0001-ENGR00268112-pcie-emaluate-the-pcie-ep-as-ram-device.patch ) since i am using a devicetree based kernel and there is no arch/arm/mach-mx6/pcie.c file in my linux src

How do i apply the patch now?

Re: iMX6q pcie interface with Xilinx device

igorpadykov — Tue, 25 Aug 2015 04:39:26 GMT

one can look at attached Linux Manual included in L3.14.28-1.0.0 GA

Chapter 42 i.MX 6 PCI Express Root Complex Driver.

Also as shows Release Notes p.11 this release (with device tree)

supports PCIe EP/RC validation system and for pcie dts configuration one can look at

linux../arch/arm/boot/dts/imx6qdl.dtsi

Best regards

igor

Re: iMX6q pcie interface with Xilinx device

lsg5131420 — Thu, 23 Jun 2016 12:28:34 GMT

i have the similar problem. i use the imx6sx-sdb board to interfacing with Xiinx Spartan-6 FPGA。I can recognize the FPGA use lspci command .

root@imx6sx_all:~# lspci

00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01)

01:00.0 Memory controller: Xilinx Corporation Default PCIe endpoint ID (rev 26)

but when i use memtool cmd write data to zhe FPGA mem space ,i failed.

root@imx6sx_all:/unit_tests# ./memtool 08100000=12345678

Writing 32-bit value 0x12345678 to address 0x08100000

root@imx6sx_all:/unit_tests#

root@imx6sx_all:/unit_tests# ./memtool 08100000 1

Reading 0x1 count starting at address 0x08100000

0x08100000: FFFFFFFF

i use the 3.14.52 BSP