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    <title>i.MX Processorsのトピックssi can't generate bit clock</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457580#M71551</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I configure ssi1 as network mode,Frame Sync and Transmit Clock generated internally,and route it to AUD3,but I can't get clock on AUD3_TXC pin and&amp;nbsp; AUD3_TXFS pin,who can help me?!!!!&lt;/P&gt;&lt;P&gt;Thanks in advance!!!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there any problem in this function?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//route ssi1 to AUD3&lt;/P&gt;&lt;P&gt;static int imx_audmux_config(int slave, int master)&lt;/P&gt;&lt;P&gt;{&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; int ret;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; unsigned int ptcr, pdcr;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; slave = slave - 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //slave=3-1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; master = master - 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //master=1-1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ptcr = MXC_AUDMUX_V2_PTCR_SYN |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TFSDIR |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TFSEL(master) |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TCLKDIR |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TCSEL(master);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ret = mxc_audmux_v2_configure_port(slave, ptcr, pdcr);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ptcr = MXC_AUDMUX_V2_PTCR_SYN;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ret = mxc_audmux_v2_configure_port(master, ptcr, pdcr);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; return 0;&lt;/P&gt;&lt;P&gt;} &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 17 Sep 2015 13:06:05 GMT</pubDate>
    <dc:creator>剑明廖</dc:creator>
    <dc:date>2015-09-17T13:06:05Z</dc:date>
    <item>
      <title>ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457580#M71551</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I configure ssi1 as network mode,Frame Sync and Transmit Clock generated internally,and route it to AUD3,but I can't get clock on AUD3_TXC pin and&amp;nbsp; AUD3_TXFS pin,who can help me?!!!!&lt;/P&gt;&lt;P&gt;Thanks in advance!!!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there any problem in this function?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//route ssi1 to AUD3&lt;/P&gt;&lt;P&gt;static int imx_audmux_config(int slave, int master)&lt;/P&gt;&lt;P&gt;{&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; int ret;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; unsigned int ptcr, pdcr;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; slave = slave - 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //slave=3-1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; master = master - 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //master=1-1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ptcr = MXC_AUDMUX_V2_PTCR_SYN |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TFSDIR |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TFSEL(master) |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TCLKDIR |&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; MXC_AUDMUX_V2_PTCR_TCSEL(master);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ret = mxc_audmux_v2_configure_port(slave, ptcr, pdcr);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ptcr = MXC_AUDMUX_V2_PTCR_SYN;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ret = mxc_audmux_v2_configure_port(master, ptcr, pdcr);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; return 0;&lt;/P&gt;&lt;P&gt;} &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Sep 2015 13:06:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457580#M71551</guid>
      <dc:creator>剑明廖</dc:creator>
      <dc:date>2015-09-17T13:06:05Z</dc:date>
    </item>
    <item>
      <title>Re: ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457581#M71552</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;can any one help me?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 Sep 2015 09:27:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457581#M71552</guid>
      <dc:creator>剑明廖</dc:creator>
      <dc:date>2015-09-21T09:27:40Z</dc:date>
    </item>
    <item>
      <title>Re: ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457582#M71553</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have you setup&amp;nbsp; "snd_soc_dai_set_sysclk" correctly?&lt;/P&gt;&lt;P&gt;For SSI master mode you need to mentioned "SND_SOC_CLOCK_OUT"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;/TD&gt;&lt;TD&gt;ret = snd_soc_dai_set_sysclk(cpu_dai, 0, bclk, SND_SOC_CLOCK_OUT);&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Saurabh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 Sep 2015 10:35:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457582#M71553</guid>
      <dc:creator>saurabh206</dc:creator>
      <dc:date>2015-09-21T10:35:02Z</dc:date>
    </item>
    <item>
      <title>Re: ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457583#M71554</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Actually, the code you listed here has no sense for me. As far as I understand, you are trying to configure the SSI1 interface to operate in master mode and to be routed out of the chip through AUD3 port. Am I right? Please clarify. Also, please specify, what exactly processor of i.MX series do you use to make me able to check the required configuration.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 22 Sep 2015 07:28:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457583#M71554</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2015-09-22T07:28:42Z</dc:date>
    </item>
    <item>
      <title>Re: ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457584#M71555</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you very much!&lt;/P&gt;&lt;P&gt;Yes,you are right.And I use I.MX6Q processor.Please help me!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Sep 2015 03:17:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457584#M71555</guid>
      <dc:creator>剑明廖</dc:creator>
      <dc:date>2015-09-25T03:17:20Z</dc:date>
    </item>
    <item>
      <title>Re: ssi can't generate bit clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457585#M71556</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am sure that I have configure the sysclk as SND_SOC_CLOCK_OUT,but it still not clock generare on aud3.&lt;/P&gt;&lt;P&gt;Please help me, thank you very much!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Sep 2015 03:19:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ssi-can-t-generate-bit-clock/m-p/457585#M71556</guid>
      <dc:creator>剑明廖</dc:creator>
      <dc:date>2015-09-25T03:19:32Z</dc:date>
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