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    <title>topic Re: IMX6DQ RGMII impedance? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ-RGMII-impedance/m-p/457177#M71411</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Driver strength and ODT of RGMII signals are configurable. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Please refer to section 36.4.487 [Pad Group Control Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;(IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM)] and of the i.MX6 DQ RM.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;“Drive strength Controlled by bits [5:3] (DSE) of the following registers &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;in IOMUXC (IOMUX controller):&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TDx (4 registers)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RDx (4 registers)”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Termination resistors are not recommended.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Also, please refer to section 9.5.1.2 (RGMII) of the “Hardware Development Guide for i.MX 6 …”&lt;BR /&gt; regarding IBIS model.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf&lt;/A&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Jul 2015 06:16:16 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2015-07-08T06:16:16Z</dc:date>
    <item>
      <title>IMX6DQ RGMII impedance?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ-RGMII-impedance/m-p/457176#M71410</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi,&lt;/P&gt;&lt;P&gt;i'm doing a design using I.MX6DQ. &lt;/P&gt;&lt;P&gt;what's impedance of the RGMII interface in I.MX6 chip? &lt;/P&gt;&lt;P&gt;does it need to add termination resistor on the RGMII tx signals? &lt;/P&gt;&lt;P&gt;I notice the Sabre board does not use them.&lt;/P&gt;&lt;P&gt;but i didn't any information in the datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Jul 2015 06:40:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ-RGMII-impedance/m-p/457176#M71410</guid>
      <dc:creator>zhiminwan</dc:creator>
      <dc:date>2015-07-07T06:40:08Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6DQ RGMII impedance?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ-RGMII-impedance/m-p/457177#M71411</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Driver strength and ODT of RGMII signals are configurable. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Please refer to section 36.4.487 [Pad Group Control Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;(IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM)] and of the i.MX6 DQ RM.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;“Drive strength Controlled by bits [5:3] (DSE) of the following registers &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;in IOMUXC (IOMUX controller):&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_TDx (4 registers)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;IOMUXC_SW_PAD_CTL_PAD_RGMII_RDx (4 registers)”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Termination resistors are not recommended.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Also, please refer to section 9.5.1.2 (RGMII) of the “Hardware Development Guide for i.MX 6 …”&lt;BR /&gt; regarding IBIS model.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A class="jive-link-external-small" href="https://community.freescale.com/external-link.jspa?url=http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf&lt;/A&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Jul 2015 06:16:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ-RGMII-impedance/m-p/457177#M71411</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-07-08T06:16:16Z</dc:date>
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