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    <title>i.MX ProcessorsのトピックRe: i.MX6SL: uSDHC Boot eFuse Descriptions</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456841#M71322</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 05 Nov 2015 03:41:49 GMT</pubDate>
    <dc:creator>norishinozaki</dc:creator>
    <dc:date>2015-11-05T03:41:49Z</dc:date>
    <item>
      <title>i.MX6SL: uSDHC Boot eFuse Descriptions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456839#M71320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Champs,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the RM ver2, BOOT_CFG2[1] looks to be allocated only for SD2.&lt;/P&gt;&lt;P&gt;This is a typo and actually true to all of 4 uSDHC ports, right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/51898iA22E31901CBB0A41/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Nov 2015 11:21:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456839#M71320</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-11-04T11:21:38Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SL: uSDHC Boot eFuse Descriptions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456840#M71321</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nori&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 5-4. SD/eSD Boot Fusemap&amp;nbsp; RM (address 0x470[7:0])&lt;/P&gt;&lt;P&gt;provides other uSDHC ports selection through fuses. GPIO option&lt;/P&gt;&lt;P&gt;only for SD2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Nov 2015 01:44:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456840#M71321</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-11-05T01:44:39Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SL: uSDHC Boot eFuse Descriptions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456841#M71322</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Nov 2015 03:41:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SL-uSDHC-Boot-eFuse-Descriptions/m-p/456841#M71322</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-11-05T03:41:49Z</dc:date>
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