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    <title>i.MX ProcessorsのトピックLPDDR2 to i.MX6 Dual Lite</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-to-i-MX6-Dual-Lite/m-p/453396#M70534</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;I'm want to add a dual rank/dual channel LPDDR2 to an i.MX6 Dual Lite.&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;This thread shows a reference design: &lt;A href="https://community.nxp.com/thread/306503"&gt;Dual-Channel LPDDR2 Routing Rules for i.MX6&lt;/A&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Is that reference design also valid for my case? Is a layout of this reference design available?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Thank you for your help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Regards,&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Frank&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 29 Apr 2015 09:00:53 GMT</pubDate>
    <dc:creator>frankambrosius</dc:creator>
    <dc:date>2015-04-29T09:00:53Z</dc:date>
    <item>
      <title>LPDDR2 to i.MX6 Dual Lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-to-i-MX6-Dual-Lite/m-p/453396#M70534</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;I'm want to add a dual rank/dual channel LPDDR2 to an i.MX6 Dual Lite.&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;This thread shows a reference design: &lt;A href="https://community.nxp.com/thread/306503"&gt;Dual-Channel LPDDR2 Routing Rules for i.MX6&lt;/A&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Is that reference design also valid for my case? Is a layout of this reference design available?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Thank you for your help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Regards,&lt;/P&gt;&lt;P style="font-size: 13px; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Frank&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Apr 2015 09:00:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-to-i-MX6-Dual-Lite/m-p/453396#M70534</guid>
      <dc:creator>frankambrosius</dc:creator>
      <dc:date>2015-04-29T09:00:53Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 to i.MX6 Dual Lite</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-to-i-MX6-Dual-Lite/m-p/453397#M70535</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, this design can be used as a reference for your case as well. Unfortunately, the layout file for this design is not publicly available. For the hardware design/layout recommendations, please refer to the i.MX6 Series Hardware Development Guide (IMX6DQ6SDLHDG) Rev.1 document, available on the Freescale web site:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;fpsp=1&amp;amp;tab=Documentation_Tab" target="_blank"&gt;http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;fpsp=1&amp;amp;tab=Documentation_Tab&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Especially, please refer to the Table 2-1 and Sections 3.1 to 3.6.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note: each 32-bit LPDDR2 channel can be routed independently of each other. Bit swapping within a byte lane/channel is not allowed by LPDDR2 JEDEC spec.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Apr 2015 09:30:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-to-i-MX6-Dual-Lite/m-p/453397#M70535</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2015-04-30T09:30:06Z</dc:date>
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