topic Re: DDR differential clock termination design rules in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/DDR-differential-clock-termination-design-rules/m-p/450295#M69773 <HTML><HEAD></HEAD><BODY><P>Hi Ko-hey</P><P></P><P>right, user needs to check "DDR Devices's Clock Signals" section P12 and P13.</P><P>Note that this app note is given as additional recommendation, so FSL documents</P><P>HW Design Checking List for i.Mx6DQSDL and IMX6DQ6SDLHDG</P><P>supersede any recommendations in that document.</P><P></P><P>Best regards</P><P>igor</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Mon, 02 Nov 2015 13:11:46 GMT igorpadykov 2015-11-02T13:11:46Z DDR differential clock termination design rules https://community.nxp.com/t5/i-MX-Processors/DDR-differential-clock-termination-design-rules/m-p/450294#M69772 <HTML><HEAD></HEAD><BODY><P>Hi all</P><P></P><P></P><P>I have a question about differential clock termination design rules.</P><P>According to the DDR section of schematics tab in following Check List,&nbsp; user have to check Micron's Technical Note.</P><P><A class="jive-link-wiki-small" data-containerid="2004" data-containertype="14" data-objectid="93819" data-objecttype="102" href="https://community.freescale.com/docs/DOC-93819">https://community.freescale.com/docs/DOC-93819</A></P><P></P><P></P><P>I have a question about it.</P><P>I think that user need to check only "DDR Devices's Clock Signals" section P12 and P13.</P><P></P><P></P><P>Is it correct ?</P><P></P><P></P><P></P><P></P><P>Ko-hey</P></BODY></HTML> Mon, 02 Nov 2015 10:28:06 GMT https://community.nxp.com/t5/i-MX-Processors/DDR-differential-clock-termination-design-rules/m-p/450294#M69772 ko-hey 2015-11-02T10:28:06Z Re: DDR differential clock termination design rules https://community.nxp.com/t5/i-MX-Processors/DDR-differential-clock-termination-design-rules/m-p/450295#M69773 <HTML><HEAD></HEAD><BODY><P>Hi Ko-hey</P><P></P><P>right, user needs to check "DDR Devices's Clock Signals" section P12 and P13.</P><P>Note that this app note is given as additional recommendation, so FSL documents</P><P>HW Design Checking List for i.Mx6DQSDL and IMX6DQ6SDLHDG</P><P>supersede any recommendations in that document.</P><P></P><P>Best regards</P><P>igor</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Mon, 02 Nov 2015 13:11:46 GMT https://community.nxp.com/t5/i-MX-Processors/DDR-differential-clock-termination-design-rules/m-p/450295#M69773 igorpadykov 2015-11-02T13:11:46Z