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    <title>i.MX ProcessorsのトピックRe: Enhanced buffer descriptors for iMX6Q</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450236#M69751</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Michael&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at attached part of older evision of RM with&lt;/P&gt;&lt;P&gt;description of enhanced buffer descriptors.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 May 2015 00:54:16 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-05-26T00:54:16Z</dc:date>
    <item>
      <title>Enhanced buffer descriptors for iMX6Q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450235#M69750</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can anyone point me to a description of the Enhanced Buffer Descriptors for the Ethernet Controller on an iMX6Q?&amp;nbsp; Section 23.6.14 of the reference manual is missing (i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014).&amp;nbsp; The reference manual for the Solo has a description of the legacy buffers, but not the enhanced.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Side question: We are developing a system sans Linux (uCOS) and are having a few issues surrounding errata ERR004512.&amp;nbsp; Does anyone knows of a handy app note or reference for the settings of the RX FIFO levels/pause frame configurations?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 May 2015 02:15:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450235#M69750</guid>
      <dc:creator>michaeledgar</dc:creator>
      <dc:date>2015-05-21T02:15:11Z</dc:date>
    </item>
    <item>
      <title>Re: Enhanced buffer descriptors for iMX6Q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450236#M69751</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Michael&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at attached part of older evision of RM with&lt;/P&gt;&lt;P&gt;description of enhanced buffer descriptors.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 May 2015 00:54:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450236#M69751</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-05-26T00:54:16Z</dc:date>
    </item>
    <item>
      <title>Re: Enhanced buffer descriptors for iMX6Q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450237#M69752</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for the information.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And as for the issues surrounding errata ERR004512, it turned out to be the switch we were connected to did have have Flow Control enabled.&amp;nbsp; Enabling flow control on the iMX and the switch solve the macerror count (FIFO overrun) from occuring.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 May 2015 01:24:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enhanced-buffer-descriptors-for-iMX6Q/m-p/450237#M69752</guid>
      <dc:creator>michaeledgar</dc:creator>
      <dc:date>2015-05-26T01:24:21Z</dc:date>
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