<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: NAND FLASH on MX6 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177636#M6974</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sorry my misstake, I was looking at an existing schematic and there it is&amp;nbsp;the SD4_CLK which is muxed with NANDF_WE and the SD4_CMD is in pinunion with NANDF_RE.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please use the pin-muxer tool from freescale to plan the pins (the rawnand section provides all pin-options for the nand).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After checking, it looks like the we/re signals are ONLY available on E16/B17&lt;/P&gt;&lt;P&gt;The hard way is to understand the iomux section in the reference manual (table 4.1 in chapter 4) and pick the best for your routing. (search for rawnand and rdn or wdn )&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 25 Jul 2012 07:43:41 GMT</pubDate>
    <dc:creator>ThiloJeremias</dc:creator>
    <dc:date>2012-07-25T07:43:41Z</dc:date>
    <item>
      <title>NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177633#M6971</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN id="result_box" lang="en" lang="en"&gt;&lt;SPAN class="hps"&gt;I&lt;/SPAN&gt;&lt;SPAN&gt;'m&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;trying to understand&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;how to use a&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;NAND&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;FLASH&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;with the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;MX6&lt;/SPAN&gt;&lt;SPAN&gt;. The reference manual explains that it's possible to use and&amp;nbsp;&lt;SPAN id="result_box" lang="en" lang="en"&gt;&lt;SPAN class="hps"&gt;asynchronous&lt;/SPAN&gt;&lt;/SPAN&gt; nand flash interface but I don't know where to find the NANDF_RE# anf NANDF_WE# signals.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2012 06:38:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177633#M6971</guid>
      <dc:creator>FelixVidal</dc:creator>
      <dc:date>2012-07-25T06:38:50Z</dc:date>
    </item>
    <item>
      <title>Re: NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177634#M6972</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Are you looking on how to access the signals from SW? or do you want to build a schematic and need to connect those sigs to the right pin?&lt;/P&gt;&lt;P&gt;In the first case, I suggest looking at the u-boot (freescale 2009) or freescale kernel (2.6.38) for the mxc nand drivers. In the latter you need to use a ping that the muxer can set to the SD?_CLK/SD?_CMD pins. &amp;nbsp;See a reference schematic for complete details. I suggest that you ask your Freescale contact for the diagrams.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;cheers&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2012 07:06:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177634#M6972</guid>
      <dc:creator>ThiloJeremias</dc:creator>
      <dc:date>2012-07-25T07:06:36Z</dc:date>
    </item>
    <item>
      <title>Re: NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177635#M6973</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'd like to build a schematic with a NAND FLASH device (not a SD memory), so I think the SDx_yyy signals are not useful for this. I'm worried because I've found all the signals I need in the reference manual (NANDF_Dx, NANDF_CLE, NANDF_ALE...) but &lt;SPAN id="result_box" lang="en" lang="en"&gt;&lt;SPAN class="hps"&gt;I&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;need to know&lt;/SPAN&gt; also &lt;SPAN class="hps"&gt;where are the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;NANDF_RE&lt;/SPAN&gt; and &lt;SPAN class="hps"&gt;NANDF_WE&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;(which&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;are essential&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;in&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;an asynchronous interface&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;of this kind)&lt;/SPAN&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN id="result_box" lang="en" lang="en"&gt;&lt;SPAN class="hps"&gt;&lt;BR class="hps" /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2012 07:18:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177635#M6973</guid>
      <dc:creator>FelixVidal</dc:creator>
      <dc:date>2012-07-25T07:18:20Z</dc:date>
    </item>
    <item>
      <title>Re: NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177636#M6974</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sorry my misstake, I was looking at an existing schematic and there it is&amp;nbsp;the SD4_CLK which is muxed with NANDF_WE and the SD4_CMD is in pinunion with NANDF_RE.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please use the pin-muxer tool from freescale to plan the pins (the rawnand section provides all pin-options for the nand).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After checking, it looks like the we/re signals are ONLY available on E16/B17&lt;/P&gt;&lt;P&gt;The hard way is to understand the iomux section in the reference manual (table 4.1 in chapter 4) and pick the best for your routing. (search for rawnand and rdn or wdn )&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2012 07:43:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177636#M6974</guid>
      <dc:creator>ThiloJeremias</dc:creator>
      <dc:date>2012-07-25T07:43:41Z</dc:date>
    </item>
    <item>
      <title>Re: NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177637#M6975</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks a lot !.&lt;/P&gt;&lt;P&gt;&lt;SPAN id="result_box" lang="en" lang="en"&gt;&lt;SPAN class="hps"&gt;It's a bit&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;confusing&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;the way it&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;is organized&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;IOMUX&lt;/SPAN&gt; &lt;SPAN&gt;in this preliminary version...&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en" lang="en"&gt;&lt;SPAN&gt;Now I have the schematic OK.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2012 08:25:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177637#M6975</guid>
      <dc:creator>FelixVidal</dc:creator>
      <dc:date>2012-07-25T08:25:24Z</dc:date>
    </item>
    <item>
      <title>Re: NAND FLASH on MX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177638#M6976</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Thilo,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I readed in the feature: IMX6 can work with&amp;nbsp;&amp;nbsp;8-bit NAND-Flash, including support for Raw MLC/SLC. But other place I readed about pin multiplexing and I see there: the raw NAND can work 16-bit NAND when I configure SD4 pins for NAND. So what do you thing about what kind of bit with (8-bit or 16-bit) FLASH can work with MX6?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks a lot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;BR /&gt; &lt;CITE&gt;Thilo Jeremias said:&lt;/CITE&gt;&lt;/P&gt;&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/nand-flash-on-mx6?groupUrl=i-mx-6-series-processors&amp;amp;#4103961Comment77105"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;Sorry my misstake, I was looking at an existing schematic and there it is&amp;nbsp;the SD4_CLK which is muxed with NANDF_WE and the SD4_CMD is in pinunion with NANDF_RE.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please use the pin-muxer tool from freescale to plan the pins (the rawnand section provides all pin-options for the nand).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After checking, it looks like the we/re signals are ONLY available on E16/B17&lt;/P&gt;&lt;P&gt;The hard way is to understand the iomux section in the reference manual (table 4.1 in chapter 4) and pick the best for your routing. (search for rawnand and rdn or wdn )&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Aug 2012 15:09:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-FLASH-on-MX6/m-p/177638#M6976</guid>
      <dc:creator>ZoltanBaranyai</dc:creator>
      <dc:date>2012-08-17T15:09:33Z</dc:date>
    </item>
  </channel>
</rss>

