i.MX Processorsのトピック2layer routing example....

2layer routing example....

albertguardiola — Thu, 02 Jul 2015 08:50:44 GMT

Hi all,

There's this "MX28_DDR2_Escape_routing_example" layout file... I really can't recall where I got it, but it's somehow related to AN4215 ("2-Layer Escape Routing Example" section).

I this layout example, I found something that I don't understand:

Pins K14 and K15 are shorted together, and L15 is tied to VDD_EMI. However: according to IMX28 pinout, the pins that do need to be shorted (EMI_DDR_OPEN and EMI_DDR_OPEN_FB) are K14 and L15, whereas K15 shall be tied to VDD_EMI (1V8).

There are others discrepancies in the IMX pinout: for instance, M11, M12 pins are connected to GND. However, according to the datasheet, those pins are to be connected to VDD...

Can anyone confirm those discrepancies?

Thanks indeed, best regards

Re: 2layer routing example....

Yuri — Thu, 02 Jul 2015 09:32:02 GMT

Please use the i.MX28 EVK design as PCB example.

According to the recent i.MX28 Datasheet

EMI_DDR_OPEN is K14 pin

EMI_DDR_OPEN_FB is L15 pin

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX28AEC.pdf

The i.MX28 EVK design uses the same pin assignment, and the trace is not very short.

The information of MX28_DDR2_Escape_Routing_Example - is incorrect and I informed

the team about it.

Have a great day,
Yuri

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Re: 2layer routing example....

albertguardiola — Thu, 02 Jul 2015 09:37:15 GMT

Thanks indeed Yuri,

That makes sense.

Best regards

Re: 2layer routing example....

albertguardiola — Fri, 03 Jul 2015 07:13:17 GMT

Hi again Yuri,

I can see that, in the EVK, DDR2 address lines are routed so that their length is approximately two times the lenght of clock and data lines. We do not understand the reason why this is done that way. As far as we know, this is not advised in usual DDR2 routing guidelines. Can you provide some information on this?

Thanks indeed.

Re: 2layer routing example....

Yuri — Mon, 06 Jul 2015 03:06:47 GMT

Basically, the best approach - to use simulation technique for PCB design.
In the same time, general rules may be provided for customers to simplify their
PCB considerations, but note, for assurance such rules are very strong.
Section 5.2 (Routing) of app note AN4215 (i.MX28 Layout and Design
Guidelines) provides general considerations regarding PCB design with i.MX28.
The EVK may violate some rules, since it was design before recommendations
were issued.

Regards,
Yuri.