<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: i.MX6 availabe PCIE memory access in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449599#M69577</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I know that Q2 works on Linux freescale 3.0.35 and i.MX6 Solo ARM processor.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Oct 2015 10:54:45 GMT</pubDate>
    <dc:creator>stjepanhenc</dc:creator>
    <dc:date>2015-10-12T10:54:45Z</dc:date>
    <item>
      <title>i.MX6 availabe PCIE memory access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449598#M69576</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;Regard to PCIe of L3.14.28 Yocto i.MX6Q SabreSD BSP, I'm confusing now.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;*&amp;nbsp; I believe i.MX6 support PCIe RC mode only so far.&lt;/P&gt;&lt;P&gt;*&amp;nbsp; According to the release note, there is PCIe EP/RC validation system.&lt;/P&gt;&lt;P&gt;*&amp;nbsp; I found a patch here:&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="95014" data-objecttype="102" href="https://community.nxp.com/docs/DOC-95014"&gt;https://community.freescale.com/docs/DOC-95014&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="544463" data-objecttype="2" href="https://community.nxp.com/message/544463#544463"&gt;https://community.freescale.com/message/544463&lt;/A&gt;&lt;/P&gt;&lt;P&gt;*&amp;nbsp; This system realized following features, I think.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EP can access the memory of RC.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RC can access the memory of EP.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me confirm some use cases as following, after patch applied;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;(Q1)&amp;nbsp; Can FPGA(EP mode) access the&amp;nbsp; 16MB memory of iMX6(RC mode)?&lt;/P&gt;&lt;P&gt;(Q2)&amp;nbsp; Can iMX6(RC mode) access the 256MB memory of FPGA(EP mode)?&lt;/P&gt;&lt;P&gt;(Q3)&amp;nbsp; Can iMX6(EP mode) access the 256MB memory of FPGA(RC mode)?&lt;/P&gt;&lt;P&gt;(Q4)&amp;nbsp; Can FPGA(RC mode) access the&amp;nbsp; 16MB memory of iMX6(EP mode)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope at least fist 2 answers are YES and BSP already supported them.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anyone help me?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Oct 2015 10:47:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449598#M69576</guid>
      <dc:creator>torus1000</dc:creator>
      <dc:date>2015-10-09T10:47:11Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 availabe PCIE memory access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449599#M69577</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I know that Q2 works on Linux freescale 3.0.35 and i.MX6 Solo ARM processor.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Oct 2015 10:54:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449599#M69577</guid>
      <dc:creator>stjepanhenc</dc:creator>
      <dc:date>2015-10-12T10:54:45Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 availabe PCIE memory access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449600#M69578</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi torus1000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to link below describing BARs limit for memory regions&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/message/334959"&gt;Re: PCIe BAR length limit&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Oct 2015 12:28:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-availabe-PCIE-memory-access/m-p/449600#M69578</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-10-19T12:28:57Z</dc:date>
    </item>
  </channel>
</rss>

