i.MX53 TZIC PRIORITY_MASK register setting

torus1000 — Tue, 18 Aug 2015 05:11:53 GMT

Hi chip experts,

I'm confusing about PRIORITY_MASK setting in TZIC of i.MX53.
I beleive highest priority is 0 but usage describe as following.

The ARM platform will
only receive an interrupt if there is a pending interrupt with a priority higher than the
value in this register. If an interrupt source asserts and its priority is equal to or lower
than the priority mask value, it will not cause an interrupt to the ARM platform.

Does "higher" mean (PRIORITYn < PRIORITY_MASK)?

Does "equal to or lower" mean (PRIORITYn >= PRIORITY_MASK)?

Can anyone clarify for me?

Thanks.

Re: i.MX53 TZIC PRIORITY_MASK register setting

igorpadykov — Tue, 18 Aug 2015 06:10:33 GMT

Hi torus1000

I believe you are right, highest priority value is 0, as describes

below part of RM

Best regards

igor

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i.MX Processorsのトピックi.MX53 TZIC PRIORITY_MASK register setting

i.MX53 TZIC PRIORITY_MASK register setting

Re: i.MX53 TZIC PRIORITY_MASK register setting