topic MIPI CSI receiver problem in i.MX Processors

MIPI CSI receiver problem

kristofferglemb — Fri, 11 Sep 2015 08:50:17 GMT

Hi everybody,

I'm doing board bring up on a board with a FPGA MIPI CSI transmitter and the IMX6 as a receiver.

I'm having some trouble getting the MIPI CSI block in the IMX6 properly receive the signals from the FPGA. I've tried at 200 MHz and 400 MHz MIPI DPHY clock rate and the problem is the same. The MIPI_CSI_PHY_STATE register goes from 0x200 (FPGA not transmitting) to 0x6F0 when the FPGA transmits data (i.e. not receiving any clock, clock and data lanes in stop state). I'm using 4 data lanes.

When operating at 200 MHz I write 0x14 to the DPHY clock register during reset. For 400 MHz I've used 0x6. Since this register is undocumented I'm unsure if these are the correct values, can you confirm?

What can cause this type of issue?

/Kristoffer

Re: MIPI CSI receiver problem

kristofferglemb — Fri, 11 Sep 2015 17:09:14 GMT

Could you please also clarify the "dphy_clk" in Linux, I think it is the IMX6 clock HSI_TX. What function does it have for MIPI CSI receiver? If any, what frequency is needed to operate at a DPHY clock rate of 200 MHz and 400 MHz ?

My "pixel_clk" (EMI_SEL) is operating at 396 MHz. In the "Debug steps for customer MIPI sensor.docx" document it is written "hsp_clk > ccm_pixel_clk/0.9 > mipi_clk/(8*2)*lanes. The default setting for pixel_clk seems to be 396 MHz but hsp_clk can max be 266 MHz according to the reference manual. Please explain what are good values for dphy_clk, pixel_clk and hsp_clk for a 400 MHz * 4 lane MIPI CSI setup.

Re: MIPI CSI receiver problem

Yuri — Mon, 14 Sep 2015 08:09:18 GMT

Hello,

The D-PHY clock is internal clock. You may use recommendations

the "Debug steps for customer MIPI sensor.docx".

Have You tried recommendations of ludovic leau-mercier in

the following thread ?

https://community.freescale.com/thread/357423

Have a great day,
Yuri

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